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MPC2104 View Datasheet(PDF) - Motorola => Freescale

Part Name
Description
Manufacturer
MPC2104 Datasheet PDF : 24 Pages
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TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
TAG RAM READ CYCLE (See Notes 1 through 4)
Tag RAM
Parameter
Symbol
Min
Max
Clock Access Time
tKHQV
10
Output Enable to Output Valid
tGLQV
8
Output Enable to Output Active
tGLQX
0
Output Disable to Q High–Z
tGHQZ
1
6
Status Bit Hold from Address Change
tAXSX
3
Address Access Time Status Bits
tAVSV
10
Tag Bit Hold from Address Change
tAVQX
3
Address Access Time Tag Bits
tAVQV
12
NOTES:
1. Set–up and hold times, W (write) referes to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag reads are asynchronous.
Unit
Notes
ns
ns
ns
ns
ns
ns
ns
ns
TAG RAM WRITE CYCLE (See Notes 1 through 4)
Tag RAM
Parameter
Symbol
Min
Max
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Output Active
Set–up Times
tKHKH
15
tKHKL
4.5
tKLKH
4.5
tKHQX
1.5
Address
tAVKH
3
Write
tWVKH
Hold Times
Address
tKHAX
1.5
Write
tKHWX
Status Output Hold
tKHSX
0
Clock High to Status Bits Valid
tKHSV
9
NOTES:
1. Set–up and hold times, W (write) referes to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag writes are synchronous.
Unit
Notes
ns
ns
ns
ns
ns
ns
ns
ns
MOTOROLA FAST SRAM
MPC2104MPC2105MPC2106MPC2107
17

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