CP2120 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
CP2120 Datasheet PDF : 24 Pages
| |||
CP2120
Table 4. SPI Slave Timing Parameters
Slave Mode Timing* (See Figure 4)
TSE
NSS Falling to First SCLK Edge
TSD
Last SCLK Edge to NSS Rising
TSEZ
NSS Falling to MISO Valid
TSDZ
NSS Rising to MISO High-Z
TCKH
SCLK High Time
TCKL
SCLK Low Time
TSIS
MOSI Valid to SCLK Sample Edge
TSIH
SCLK Sample Edge to MOSI Change
TSOH
SCLK Shift Edge to MISO Change
TSLH
Last SCLK Edge to MISO Change
(CKPHA = 1 ONLY)
*Note: TSYSCLK equals 24.5 MHz.
2 x TSYSCLK
2 x TSYSCLK
—
—
5 x TSYSCLK
5 x TSYSCLK
2 x TSYSCLK
2 x TSYSCLK
—
6 x TSYSCLK
—
ns
—
ns
4 x TSYSCLK ns
4 x TSYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x TSYSCLK ns
8 x TSYSCLK ns
5.5. I2C Activity During SPI Transactions
If the SPI Master attempts to transmit a command to the CP2120 while the I2C bus is inactive, the CP2120 will
disable its slave response. If an I2C Master device on the bus attempts to address the CP2120 during this time, the
CP2120 will not ACK the address defined in the I2CADR Internal Register.
If the SPI Master attempts to transmit a command to the CP2120 while the CP2120 is acting as the Master on the
I2C bus, the CP2120 will suspend I2C bus activity until the SPI Master has completed transmission of the
command. For instance, if the SPI Master calls the Read Internal Register command while the CP2120 is in the
middle of an I2C transaction, that I2C transaction will stall until the CP2120 completely processes the Read Internal
Register command.
12
Rev. 1.0
Share Link: 