CP2120 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
CP2120 Datasheet PDF : 24 Pages
| |||
CP2120
Internal Register Definition 1. I2CCLOCK: I2C Clock Frequency Configuration
R/W
I2CCK7
Bit 7
R/W
I2CCK6
Bit 6
R/W
I2CCK5
Bit 5
R/W
I2CCK4
Bit 4
R/W
I2CCK3
Bit3
R/W
I2CCK2
Bit 2
R/W
I2CCK1
Bit 1
R/W
I2CCK0
Bit 0
Internal Register Address:
Reset Value:
Bit 7-0:
0x02
0xA0
I2CCK7-0: I2C Clock Frequency Configuration value (minimum register value = 5,
maximum register value = 255)
The transaction time-out counter, which terminates an I2C transaction after a set period of time has passed, can be
configured through the I2CTO Internal Register. If the time-out counter is not enabled, the CP2120 will make only
one attempt at executing an I2C transaction and abort if that transaction attempt fails.
Time-out Frequency = 1-T---2-O--8--Hz
Equation 2. CTO Time-Out Frequency
Internal Register Definition 2. I2CTO: I2C Time Out
R/W
TO6
Bit 7
R/W
TO5
Bit 6
R/W
TO4
Bit 5
R/W
TO3
Bit 4
R/W
TO2
Bit3
R/W
TO1
Bit 2
R/W
TO0
Bit 1
R/W
TEN
Bit 0
Internal Register Address:
Reset Value:
Bit 7-1:
Bit 0:
0x03
0x00
TO6-0: Time Out Value
TEN:Time Out Enable Bit.
0: Disable Timer.
1: Enable Timer.
The SPI Master can assign an I2C address to the CP2120 by writing to the I2CADR Internal Register. Setting this
address is not necessary for device operation. If set, the CP2120 will ACK this address when another I2C Master
on the bus attempts to communicate with it. The CP2120 will NACK all attempts at data transfer when responding
as an I2C slave.
Internal Register Definition 3. I2CADR: I2C Address
R/W
I2CAD7
Bit 7
R/W
I2CAD6
Bit 6
R/W
I2CAD5
Bit 5
R/W
I2CAD4
Bit 4
Internal Register Address:
Reset Value:
Bit 7-Bit 0:
0x05
0x00
I2CAD7-0: I2C Address
Sets I2C bus address.
R/W
I2CAD3
Bit3
R/W
I2CAD2
Bit 2
R/W
I2CAD1
Bit 1
R/W
I2CAD0
Bit 0
14
Rev. 1.0
Share Link: 