CP2120 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
CP2120 Datasheet PDF : 24 Pages
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CP2120
Internal Register Definition 8. IOCONFIG2: Port I/O Configuration 2
R/W
PCIO7.1
Bit 7
R/W
PCIO7.0
Bit 6
R/W
PCIO6.1
Bit 5
R/W
PCIO6.0
Bit 4
R/W
PCIO5.1
Bit3
R/W
PCIO5.0
Bit 2
R/W
PCIO4.1
Bit 1
R/W
PCIO4.0
Bit 0
Internal Register Address: 0x07
Reset Value: 0x00
Bit 7-6: PCIO7.1-PCIO7.0: Port Configuration for GPIO Pin 7
Bit 5-4: PCIO6.1-PCIO6.0: Port Configuration for GPIO Pin 6
Bit 3-2: PCIO5.1-PCIO5.0: Port Configuration for GPIO Pin 5
Bit 1-0: PCIO4.1-PCIO4.0: Port Configuration for GPIO Pin 4
These bits select the port state for GPIO pins 7 through 4.
PCIOx.1
0
0
1
1
PCIOx.0 GPIO Pin x Mode
0
Open Drain Output
1
Input Only
0
Push-Pull Output
1
Input Only
Internal Register Definition 9. IOSTATE: Port I/O State
R/W
GPIO7
Bit 7
R/W
GPIO6
Bit 6
R/W
GPIO5
Bit 5
R/W
GPIO4
Bit 4
R/W
GPIO3
Bit3
R/W
GPIO2
Bit 2
Internal Register Address:
Reset Value:
Bit 7-0:
0x01
0x00
GPIO7-0: General Purpose Input/Output State
Write - Output appears on output pins.
0: GPIOx set to logic low output.
1: GPIO set to logic high output.
Read - Reads port state.
0: GPIOx is logic low.
1: GPIOx is logic high.
R/W
GPIO1
Bit 1
R/W
GPIO0
Bit 0
20
Rev. 1.0
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