CP2120 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
CP2120 Datasheet PDF : 24 Pages
| |||
CP2120
7. Port I/O
The CP2120 offers eight general-purpose port pins that can be configured as output, input, or quasi-bidirectional
output by writing to the internal registers, IOCONFIG and IOCONFIG2. Pin state can be updated by writing to the
internal register, IOSTATE. Reading the IOSTATE Internal Register will return the current values of each port pin.
The port pin, EINT, can be configured as an edge-triggered interrupt source by writing to the EDGEINT Internal
Register. The EIT bit sets the interrupt to trigger upon a 0 to 1 or a 1 to 0 logic change on the pin. The bit, EIE,
enables the pin as an interrupt source.
Once the interrupt has been configured and enabled, the CP2120 will pull the INT pin low when the port pin's logic
value switches to “1'” or “0”, depending on the interrupt configuration specified in the EIT bit. When an interrupt is
triggered, EIF in the EDGEINT Internal Register is set. Reading from EDGEINT will clear the EIF bit.
Internal Register Definition 7. IOCONFIG: Port I/O Configuration
R/W
PCIO3.1
Bit 7
R/W
PCIO3.0
Bit 6
R/W
PCIO2.1
Bit 5
R/W
PCIO2.0
Bit 4
R/W
PCIO1.1
Bit3
R/W
PCIO1.0
Bit 2
R/W
PCIO0.1
Bit 1
R/W
PCIO0.0
Bit 0
Internal Register Address: 0x00
Reset Value: 0x00
Bit 7-6: PCIO3.1-PCIO3.0: Port Configuration for GPIO Pin 3
Bit 5-4: PCIO2.1-PCIO2.0: Port Configuration for GPIO Pin 2
Bit 3-2: PCIO1.1-PCIO1.0: Port Configuration for GPIO Pin 1
Bit 1-0: PCIO0.1-PCIO0.0: Port Configuration for GPIO Pin 0
These bits select the port state for GPIO pins 3 through 0.
PCIOx.1
0
0
1
1
PCIOx.0 GPIO Pin x Mode
0
Open Drain Output
1
Input Only
0
Push-Pull Output
1
Reserved
Rev. 1.0
19
Share Link: 