DS17285(1998) View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated
Part Name
Description
Manufacturer
DS17285 Datasheet PDF : 32 Pages
| |||
DS17285/DS17287
UF – The Update Ended Interrupt Flag (UF) bit is set
after each update cycle. When the UIE bit is set to one,
the one in UF causes the IRQF bit to be a one which will
assert the IRQ pin. UF is cleared by reading Register C.
BIT 3 THROUGH BIT 0 – These are unused bits of the
status Register C. These bits always read zero and can-
not be written.
REGISTER D
MSB
BIT 7 BIT 6 BIT 5
VRT
0
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
LSB
BIT 0
0
VRT – The Valid RAM and Time (VRT) bit indicates the
condition of the battery connected to the VBAT pin or the
battery connected to VBAUX, whichever is at a higher
voltage. This bit is not writable and should always be a
one when read. If a zero is ever present, an exhausted
lithium energy source is indicated and both the contents
of the RTC data and RAM data are questionable.
BIT 6 THROUGH BIT 0 – The remaining bits of Register
D are not usable. They cannot be written and, when
read, they will always read zero.
EXTENDED FUNCTIONS
The extended functions provided by the
DS17285/DS17287 that are new to the RAMified RTC
family are accessed via a software controlled bank
switching scheme, as illustrated in Figure 4. In bank 0,
the clock/calendar registers and 50 bytes of user RAM
are in the same locations as for the DS1287. As a result,
existing routines implemented within BIOS, DOS, or
application software packages can gain access to the
DS17285/DS17287 clock registers with no changes.
Also in bank 0, an extra 64 bytes of RAM are provided at
addresses just above the original locations for a total of
114 directly addressable bytes of user RAM.
When bank 1 is selected, the clock/calendar registers
and the original 50 bytes of user RAM still appear as
bank 0. However, the Dallas registers which provide
control and status for the extended functions will be
accessed in place of the additional 64 bytes of user
RAM. The major extended functions controlled by the
Dallas registers are listed below:
1. 64–bit Silicon Serial Number
2. Century counter
3. Date Alarm
4. Auxiliary Battery Control/Status
5. Wake Up
6. Kickstart
7. RAM Clear Control/Status
8. 2K bytes Extended RAM Access
The bank selection is controlled by the state of the DV0
bit in register A. To access bank 0 the DV0 bit should be
written to a 0. To access bank 1, DV0 should be written
to a 1. Register locations designated as reserved in the
bank 1 map are reserved for future use by Dallas Semi-
conductor. Bits in these locations cannot be written and
will return a 0 if read.
030598 12/32
Share Link: 