DS17285(1998) View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated
Part Name
Description
Manufacturer
DS17285 Datasheet PDF : 32 Pages
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DS17285/DS17287
RF – Ram Clear Flag. This bit will be set to a logic 1
when a high to low transition occurs on the RCLR input if
RCE=1. The RF bit is cleared by writing it to a logic 0.
This bit can also be written to a logic 1 to force an inter-
rupt condition.
WF – Wake up Alarm Flag – This bit is set to 1 when a
wake up alarm condition occurs or when the user writes
it to a 1. WF is cleared by writing it to a 0.
KF – Kickstart Flag – This bit is set to a 1 when a kick-
start condition occurs or when the user writes it to a 1.
This bit is cleared by writing it to a logic 0.
EXTENDED CONTROL REGISTER 4B
MSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
ABE E32K CS RCE PRS RIE WIE
LSB
BIT 0
KSE
ABE – Auxiliary Battery Enable. This bit when written to
a logic 1 will enable the VBAUX pin for extended func-
tions.
E32K – Enable 32.768 KHz output. This bit when writ-
ten to a logic 1 will enable the 32.768 KHz oscillator fre-
quency to be output on the SQW pin. E32K is set to a
one when VCC is powered up.
CS – Crystal Select Bit. When CS is set to a 0, the oscil-
lator is configured for operation with a crystal that has a
6 pF specified load capacitance. When CS=1, the oscil-
lator is configured for a 12.5 pF crystal.
RCE – RAM Clear Enable bit. When set to a 1, this bit
enables a low level on RCLR to clear all 114 bytes of
user RAM. When RCE = 0, RCLR and the RAM clear
function are disabled.
PRS – PAB Reset Select Bit. When set to a 0 the PWR
pin will be set hi–Z when the DS17285 goes into power
fail. When set to a 1, the PWR pin will remain active
upon entering power fail.
RIE – Ram Clear Interrupt Enable. When RIE is set to a
1, the IRQ pin will be driven low when a RAM clear func-
tion is completed.
WIE – Wake Up Alarm Interrupt Enable. When VCC
voltage is absent and WIE is set to a 1, the PWR pin will
be driven active low when a wake up condition occurs,
causing the WF bit to be set to 1. When VCC is then
applied, the IRQ pin will also be driven low. If WIE is set
while system power is applied, both IRQ and PWR will
be driven low in response to WF being set to 1. When
WIE is cleared to a 0, the WF bit will have no effect on the
PWR or IRQ pins.
KSE – Kickstart Interrupt Enable. When VCC voltage is
absent and KSE is set to a 1, the PWR pin will be driven
active low when a kickstart condition occurs (KS pulsed
low), causing the KF bit to be set to 1. When VCC is then
applied, the IRQ pin will also be driven low. If KSE is set
to 1 while system power is applied, both IRQ and PWR
will be driven low in response to KF being set to 1. When
KSE is cleared to a 0, the KF bit will have no effect on the
PWR or IRQ pins.
* Reserved bits. These bits are reserved for future use
by Dallas Semiconductor. They can be read and writ-
ten, but have no effect on operation.
SYSTEM MAINTENANCE INTERRUPT (SMI)
RECOVERY STACK
An SMI recovery register stack is located in the
extended register bank, locations 4Eh and 4Fh. This
register stack, shown below, can be used by the BIOS to
recover from an SMI occurring during an RTC read or
write.
RTC ADDRESS
RTC ADDRESS – 1
4Eh
RTC ADDRESS – 2
4Fh
RTC ADDRESS – 3
SMI RECOVERY STACK
7
6
5
4
3
2
1
0
DV0 AD6 AD5 AD4 AD3 AD2 AD1 AD0
REGISTER BIT DEFINITION
030598 17/32
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