DS17285(1998) View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated
Part Name
Description
Manufacturer
DS17285 Datasheet PDF : 32 Pages
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DS17285/DS17287
viously inactive as the result of power being applied by
some means other than wake up or kickstart.
The system may be powered down under software con-
trol by setting the PAB bit to a logic 1. This causes the
open-drain PWR pin to be placed in a high impedance
state, as shown at the beginning of interval 4 in the tim-
ing diagram. As VCC voltage decays, the IRQ output pin
will be placed in a high impedance state when VCC goes
below VPF. If the system is to be again powered on in
response to a wake up or kickstart, then the both the WF
and KF flags should be cleared and WIE and/or KSE
should be enabled prior to setting the PAB bit.
During interval 5, the system is fully powered down.
Battery backup of the clock calendar and nonvolatile
RAM is in effect and IRQ is tri-stated, and monitoring of
wake up and kickstart takes place. If PRS=1, PWR
stays active, otherwise if PRS=0 PWR is tri–stated.
RAM CLEAR
The DS17285/DS17287 provides a RAM clear function
for the 114 bytes of user RAM. When enabled, this func-
tion can be performed regardless of the condition of the
VCC pin.
The RAM clear function is enabled or disabled via the
RAM Clear Enable bit (RCE; bank 1, register 04BH).
When this bit is set to a logic 1, the 114 bytes of user
RAM will be cleared (all bits set to 1) when an active low
transition is sensed on the RCLR pin. This action will
have no effect on either the clock/calendar settings or
upon the contents of the extended RAM. The RAM clear
Flag (RF, bank 1, register 04AH) will be set when the
RAM clear operation has been completed. If VCC is
present at the time of the RAM clear and RIE=1, the IRQ
line will also be driven low upon completion. The inter-
rupt condition can be cleared by writing a zero to the RF
bit. The IRQ line will then return to its inactive high level
provided there are no other pending interrupts. Once
the RCLR pin is activated, all read/write accesses are
locked out for a minimum recover time, specified as
tREC in the Electrical Characteristics section.
When RCE is cleared to zero, the RAM clear function is
disabled. The state of the RCLR pin will have no effect
on the contents of the user RAM, and transitions on the
RCLR pin have no effect on RF.
EXTENDED CONTROL REGISTERS
Two extended control registers are provided to supply
controls and status information for the extended fea-
tures offered by the DS17285/DS17287. These are
designated as extended control registers 4A and 4B and
are located in register bank 1, locations 04AH and
04BH, respectively. The functions of the bits within
these registers are described as follows.
EXTENDED CONTROL REGISTER 4A
MSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
VRT2 INCR BME
*
PAB RF WF
LSB
BIT 0
KF
VRT2 – This status bit gives the condition of the auxil-
iary battery. It is set to a logic 1 condition when the exter-
nal lithium battery is connected to the VBAUX. If this bit is
read as a logic 0, the external battery should be
replaced.
INCR – Increment in Progress status bit. This bit is set
to a 1 when an increment to the time/date registers is in
progress and the alarm checks are being made. INCR
will be set to a 1 at 122 µs before the update cycle starts
and will be cleared to 0 at the end of each update cycle.
BME – Burst Mode Enable. The burst mode enable bit
allows the extended user RAM address registers to
automatically increment for consecutive reads and
writes. When BME is set to a logic one, the automatic
incrementing will be enabled and when BME is set to a
logic zero, the automatic incrementing will be disabled.
PAB – Power Active Bar control bit. When this bit is 0,
the PWR pin is in the active low state. When this bit is 1,
the PWR pin is in the high impedance state. This bit can
be written to a logic 1 or 0 by the user. If either WF AND
WIE = 1 OR KF AND KSE = 1, the PAB bit will be cleared
to 0.
030598 16/32
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