DSP56303UM View Datasheet(PDF) - Freescale Semiconductor
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DSP56303UM Datasheet PDF : 108 Pages
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AC Electrical Characteristics
Table 2-8. SRAM Read and Write Accesses (Continued)
100 MHz
No.
Characteristics
Symbol
Expression1
Unit
Min Max
111 WR deassertion to data high impedance
—
0.25 × TC + 0.2
—
2.7
ns
[1 ≤WS ≤3]
1.25 × TC + 0.2
—
12.7 ns
[4 ≤WS ≤7]
2.25 × TC + 0.2
[WS > 8]
—
22.7 ns
112 Previous RD deassertion to data active (write)
—
1.25 × TC – 4.0
8.5
—
ns
[1 ≤WS ≤3]
2.25 × TC – 4.0
[4 ≤WS ≤7]
18.5
—
ns
3.25 × TC – 4.0
[WS > 8]
28.5
—
ns
113 RD deassertion time
—
0.75 × TC −4.0
3.5
—
ns
[1 ≤WS ≤3]
1.75 × TC −4.0
[4 ≤WS ≤7]
13.5
—
ns
2.75 × TC −4.0
[WS ≥ 8]
23.5
—
ns
114 WR deassertion time
—
0.5 × TC −4.0
1.0
—
ns
[WS = 1]
TC −4.0
[2 ≤WS ≤3]
6.0
—
ns
2.5 × TC −4.0
[4 ≤WS ≤7]
21.0
—
ns
3.5 × TC −4.0
[WS ≥ 8]
31.0
—
ns
115 Address valid to RD assertion
116 RD assertion pulse width
117 RD deassertion to address not valid
118 TA setup before RD or WR deassertion4
119 TA hold after RD or WR deassertion
—
0.5 × TC −4.0
1.0
—
ns
—
(WS + 0.25) × TC −4.0
8.5
—
ns
—
0.25 × TC −2.0
0.5
—
ns
[1 ≤WS ≤3]
1.25 × TC −2.0
[4 ≤WS ≤7]
10.5
—
ns
2.25 × TC −2.0
[WS ≥ 8]
20.5
—
ns
—
0.25 × TC + 2.0
4.5
—
ns
—
—
0
—
ns
Notes: 1. WS is the number of wait states specified in the BCR. An expression is used to compute the number listed as the minimum or
maximum value, as appropriate.
2. Timings 100, 107 are guaranteed by design, not tested.
3. All timings for 100 MHz are measured from 0.5 × Vcc to 0.5 × Vcc.
4. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted.
5. VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100°C, CL = 50 pF
Freescale Semiconductor
DSP56303 Technical Data, Rev. 11
2-13
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