DSP56303UM View Datasheet(PDF) - Freescale Semiconductor
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DSP56303UM Datasheet PDF : 108 Pages
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Specifications
Table 2-9. DRAM Page Mode Timings, Three Wait States1,2,3
100 MHz
No.
Characteristics
Symbol
Expression4
Unit
Min Max
131 Page mode cycle time for two consecutive accesses of the same
direction
4 × TC
40.0
—
ns
Page mode cycle time for mixed (read and write) accesses
tPC
3.5 × TC
35.0
—
ns
132 CAS assertion to data valid (read)
tCAC
2 × TC −5.7
—
14.3 ns
133 Column address valid to data valid (read)
tAA
3 × TC −5.7
—
24.3 ns
134 CAS deassertion to data not valid (read hold time)
tOFF
0.0
—
ns
135 Last CAS assertion to RAS deassertion
tRSH
2.5 × TC −4.0
21.0
—
ns
136 Previous CAS deassertion to RAS deassertion
tRHCP
4.5 × TC −4.0
41.0
—
ns
137 CAS assertion pulse width
138 Last CAS deassertion to RAS assertion5
• BRW[1–0] = 00, 01—not applicable
• BRW[1–0] = 10
• BRW[1–0] = 11
tCAS
tCRP
2 × TC −4.0
—
4.75 × TC −6.0
6.75 × TC −6.0
16.0
—
ns
—
—
—
41.5
—
ns
61.5
—
ns
139 CAS deassertion pulse width
tCP
1.5 × TC −4.0
11.0
—
ns
140 Column address valid to CAS assertion
tASC
TC −4.0
6.0
—
ns
141 CAS assertion to column address not valid
tCAH
2.5 × TC −4.0
21.0
—
ns
142 Last column address valid to RAS deassertion
tRAL
4 × TC −4.0
36.0
—
ns
143 WR deassertion to CAS assertion
tRCS
1.25 × TC −4.0
8.5
—
ns
144 CAS deassertion to WR assertion
tRCH
0.75 × TC −4.0
3.5
—
ns
145 CAS assertion to WR deassertion
tWCH
2.25 × TC −4.2
18.3
—
ns
146 WR assertion pulse width
tWP
3.5 × TC −4.5
30.5
—
ns
147 Last WR assertion to RAS deassertion
tRWL
3.75 × TC −4.3
33.2
—
ns
148 WR assertion to CAS deassertion
tCWL
3.25 × TC −4.3
28.2
—
ns
149 Data valid to CAS assertion (write)
tDS
0.5 × TC – 4.5
0.5
—
ns
150 CAS assertion to data not valid (write)
tDH
2.5 × TC −4.0
21.0
—
ns
151 WR assertion to CAS assertion
tWCS
1.25 × TC −4.3
8.2
—
ns
152 Last RD assertion to RAS deassertion
tROH
3.5 × TC −4.0
31.0
—
ns
153 RD assertion to data valid
154 RD deassertion to data not valid6
tGA
2.5 × TC −5.7
—
19.3 ns
tGZ
0.0
—
ns
155 WR assertion to data active
0.75 × TC – 1.5
6.0
—
ns
156 WR deassertion to data high impedance
0.25 × TC
—
2.5
ns
Notes: 1. The number of wait states for Page mode access is specified in the DRAM Control Register.
2. The refresh period is specified in the DRAM Control Register.
3. The asynchronous delays specified in the expressions are valid for the DSP56303.
4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 4 ×
TC for read-after-read or write-after-write sequences). An expression is used to compute the number listed as the minimum or
maximum value listed, as appropriate.
5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-
access.
6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
2-16
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
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