Specifications
A[0–17]
AA[0–3]
RD
WR
100
113
116
117
105
106
104
118
119
TA
D[0–23]
Note: Address lines A[0–17] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
Figure 2-12. SRAM Read Access
Data
In
A[0–17]
AA[0–3]
WR
RD
101
114
100
107
102
118
TA
108
D[0–23]
Note: Address lines A[0–17] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
Figure 2-13. SRAM Write Access
Data
Out
103
119
109
2-14
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor