DSP56303UM View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56303UM

24-Bit Digital Signal Processor

Freescale Semiconductor 

Specifications

Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States1,2 (Continued)

100 MHz

No.

Characteristics

Symbol

Expression3

Unit

Min Max

172 RAS assertion to row address not valid

tRAH

1.75 × TC −4.0

13.5

—

ns

173 Column address valid to CAS assertion

tASC

0.75 × TC −4.0

3.5

—

ns

174 CAS assertion to column address not valid

tCAH

5.25 × TC −4.0

48.5

—

ns

175 RAS assertion to column address not valid

tAR

7.75 × TC −4.0

73.5

—

ns

176 Column address valid to RAS deassertion

tRAL

6 × TC −4.0

56.0

—

ns

177 WR deassertion to CAS assertion

178 CAS deassertion to WR4 assertion

179 RAS deassertion to WR4 assertion

tRCS

tRCH

tRRH

3.0 × TC −4.0

1.75 × TC – 3.7

0.25 × TC −2.0

26.0

—

ns

13.8

—

ns

0.5

—

ns

180 CAS assertion to WR deassertion

tWCH

5 × TC −4.2

45.8

—

ns

181 RAS assertion to WR deassertion

tWCR

7.5 × TC −4.2

70.8

—

ns

182 WR assertion pulse width

tWP

11.5 × TC −4.5

110.5 —

ns

183 WR assertion to RAS deassertion

tRWL

11.75 × TC −4.3

113.2 —

ns

184 WR assertion to CAS deassertion

tCWL

10.25 × TC −4.3

98.2

—

ns

185 Data valid to CAS assertion (write)

tDS

5.75 × TC −4.0

53.5

—

ns

186 CAS assertion to data not valid (write)

tDH

5.25 × TC −4.0

48.5

—

ns

187 RAS assertion to data not valid (write)

tDHR

7.75 × TC −4.0

73.5

—

ns

188 WR assertion to CAS assertion

tWCS

6.5 × TC −4.3

60.7

—

ns

189 CAS assertion to RAS assertion (refresh)

tCSR

1.5 × TC −4.0

11.0

—

ns

190 RAS deassertion to CAS assertion (refresh)

tRPC

2.75 × TC −4.0

23.5

—

ns

191 RD assertion to RAS deassertion

tROH

11.5 × TC −4.0

111.0 —

ns

192 RD assertion to data valid

193 RD deassertion to data not valid5

tGA

10 × TC −7.0

—

93.0 ns

tGZ

0.0

—

ns

194 WR assertion to data active

0.75 × TC – 1.5

6.0

—

ns

195 WR deassertion to data high impedance

0.25 × TC

—

2.5

ns

Notes: 1. The number of wait states for an out-of-page access is specified in the DRAM Control Register.

2. The refresh period is specified in the DRAM Control Register.

3. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±) .

4. Either tRCH or tRRH must be satisfied for read cycles.

5. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.

2-20

DSP56303 Technical Data, Rev. 11

Freescale Semiconductor

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