Specifications
Table 2-4. Internal Clocks (Continued)
Characteristics
Symbol
Min
Expression
Typ
Internal clock low period
• With DPLL disabled
• With DPLL enabled
TL
—
ETC
0.49 × TC
—
Note:
Ef = External frequency; MF = Multiplication Factor = MFI + MFN/MFD; PDF = Predivision Factor;
DF = Division Factor; TC = Internal clock cycle; ETC = External clock cycle; TH = Internal clock high;
TL = Internal clock low
Max
—
0.51 × TC
2.4.2 External Clock Operation
The DSP56321 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip
oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; an example is
shown in Figure 2-1.
EXTAL
XTAL
R
C
XTAL1
C
Fundamental Frequency
Crystal Oscillator
Suggested Component Values:
fOSC = 16–32 MHz
R = 1 MΩ ± 10%
C = 10 pF ± 10%
Calculations are for a 16–32 MHz crystal with the following parameters:
• shunt capacitance (C0) of 5.2–7.3 pF,
• series resistance of 5–15 Ω, and
• drive level of 2 mW.
Note: Make sure that in the PCTL Register:
• XTLD (bit 2) = 0
Figure 2-1. Crystal Oscillator Circuits
Table 2-5. External Clock Operation
No.
Characteristics
1 Frequency of EXTAL
(EXTAL Pin Frequency)1
• With DPLL disabled
• With DPLL enabled2
2 EXTAL input high3
• With DPLL disabled
(46.7%–53.3% duty
cycle4)
• With DPLL enabled
(42.5%–57.5% duty
cycle4)
3 EXTAL input low4
• With DPLL disabled
(46.7%–53.3% duty
cycle4)
• With DPLL enabled
(42.5%–57.5% duty
cycle4)
Symbol
200 MHz
Min
Max
220 MHz
Min
Max
240 MHz
Min
Max
275 MHz
Min
Max
Ef
0 MHz
DEFR = PDF 16 MHz
× PDFR
200 MHz
200 MHz
0 MHz
16 MHz
220 MHz
220 MHz
0 MHz
16 MHz
240 MHz
240 MHz
0 MHz
16 MHz
275 MHz
275 MHz
ETH
2.34 ns
∞
2.12 ns
∞
1.95 ns
∞
1.70 ns
∞
2.13 ns 35.9 ns 1.93 ns 35.9 ns 1.77 ns 35.9 ns 1.55 ns 35.9 ns
ETL
2.34 ns
∞
2.12ns
∞
1.95 ns
∞
1.70 ns
∞
2.13 ns 35.9 ns 1.93 ns 35.9 ns 1.77 ns 35.9 ns 1.55 ns 35.9 ns
DSP56321 Technical Data, Rev. 11
2-4
Freescale Semiconductor