DSP56321 View Datasheet(PDF) - Freescale Semiconductor
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DSP56321 Datasheet PDF : 84 Pages
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AC Electrical Characteristics
2.4.5 External Memory Expansion Port (Port A)
2.4.5.1 SRAM Timing
Table 2-8. SRAM Timing
No. Characteristics Symbol
Expression1
200 MHz 220 MHz 240 MHz 275 MHz
Unit
Min Max Min Max Min Max Min Max
100 Address valid and AA
assertion pulse width2
tRC, tWC (WS + 2) × TC −4.0 21.0
18.8
16.9
15.0
ns
[3 ≤WS ≤7]
(WS + 3) × TC −4.0 51.0 — 46.0 — 41.9 — 36.0 — ns
[WS ≥ 8]
101 Address and AA valid to
tAS
WR assertion
0.75 × TC – 3.0
[WS = 3]
1.25 × TC – 3.0
[WS ≥ 4]
0.75 — 0.41 — 0.13 — –0.27 — ns
3.25 — 2.69 — 2.21 — 1.54 — ns
102 WR assertion pulse width
tWP
WS × TC −4.0
11.0 — 9.65 — 8.51 — 6.9 — ns
[WS = 3]
(WS −0.5) × TC −4.0 13.5 — 11.93 — 10.6 — 8.72 — ns
[WS ≥ 4]
103 WR deassertion to
address not valid
tWR
1.25 × TC −4.0
2.25 — 1.69 — 1.21 — 0.54 — ns
[3 ≤WS ≤7]
2.25 × TC −4.0
[WS ≥ 8]
7.25 — 6.24 — 5.38 — 4.18 — ns
104 Address and AA valid to tAA, tAC (WS + 0.75) × TC −5.8 — 12.9 — 11.2 — 9.8 — 7.84 ns
input data valid
[WS ≥ 3]
105 RD assertion to input data
tOE
(WS + 0.25) × TC −6.5 — 9.75 — 8.29 — 7.05 — 5.31 ns
valid
[WS ≥ 3]
106 RD deassertion to data
not valid (data hold time)
tOHZ
0.0 — 0.0 — 0.0 — 0.0 — ns
107 Address valid to WR
deassertion2
tAW
(WS + 0.75) × TC −4.0 14.75 — 13.06 — 11.64 — 9.63 — ns
[WS ≥ 3]
108 Data valid to WR
tDS (tDW) (WS −0.25) × TC −5.4 8.35 — 7.11 — 6.07 —
4.6
— ns
deassertion (data setup
[WS ≥ 3]
time)
109 Data hold time from WR
tDH
deassertion
1.25 × TC −4.0
[3 ≤WS ≤7]
2.25 × TC −4.0
[WS ≥ 8]
2.25 — 1.69 — 1.21 — 0.54 — ns
7.25 — 6.23 — 5.38 — 4.18 — ns
110 WR assertion to data
active
—
0.25 × TC −4.0
[WS = 3]
–2.75 — –2.86 — –2.96 — –3.1 — ns
–0.25 × TC −4.0
[WS ≥ 4]
–5.25 — –5.14 — –5.04 — –4.91 — ns
111 WR deassertion to data
—
high impedance
1.25 × TC
6.25 — 5.69 — 5.21 — 4.55 — ns
112 Previous RD deassertion
—
to data active (write)
2.25 × TC −4.0
7.25 — 6.23 — 5.38 — 4.18 — ns
113 RD deassertion time
—
114 WR deassertion time4
—
1.75 × TC −3.0
[3 ≤WS ≤7]
2.75 × TC −3.0
[WS ≥ 8]
2.0 × TC −3.0
[3 ≤WS ≤7]
3.0 × TC −3.0
[WS ≥ 8]
5.75 — 4.96 — 4.3 — 3.36 — ns
10.75 — 9.51 — 8.47 — 7.0 — ns
7.0 — 6.1 — 5.3 — 4.27 — ns
12.0 — 10.6 — 9.5 — 7.91 — ns
Freescale Semiconductor
DSP56321 Technical Data, Rev. 11
2-11
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