DSP56321 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56321

24-Bit Digital Signal Processor

Freescale Semiconductor 

Specifications

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing5 (CONTINUED)

No.

Characteristics

Expression

200 MHz

Min Max

220 MHz

Min Max

240 MHz

Min Max

275 MHz

Unit

Min Max

Notes: 1. When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to

prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended

when fast interrupts are used. Long interrupts are recommended for Level-sensitive mode.

2. This timing depends on several settings:

• For DPLL disable, using internal oscillator (DPLL Control Register (PCTL) Bit 2 = 0) and oscillator disabled during Stop (PCTL

Bit 1 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the

Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set,

it is not recommended, and these specifications do not guarantee timings for that case.

• For DPLL disable, using internal oscillator (PCTL Bit 2 = 0) and oscillator enabled during Stop (PCTL Bit 1 = 1), no stabilization

delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).

• For DPLL disable, using external clock (PCTL Bit 2 = 1), no stabilization delay is required and recovery time is defined by the

PCTL Bit 1 and Operating Mode Register Bit 6 settings.

• For DPLL enable, if PCTL Bit 1 is 0, the DPLL is shut down during Stop. Recovering from Stop requires the DPLL to lock. The

DPLL lock procedure duration is defined in Table 2-6 and will be refined after silicon characterization. This procedure is followed

by the stop delay counter. Stop recovery ends when the stop delay counter completes its count.

• The DPLT value for DPLL disable is 0.

3. Periodically sampled and not 100 percent tested.

4. For an external clock generator, RESET duration is measured while RESET is asserted, VCC is valid, and the EXTAL input is

active and valid.

For an internal oscillator, RESET duration is measured while RESET is asserted and VCC is valid. The specified timing reflects

the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other

components connected to the oscillator and reflects worst case conditions.

When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the

device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize

this state to the shortest possible duration.

5. VCCQH = 3.3 V ± 0.3 V, VCCQL = 1.6 V ± 0.1 V; TJ = –40°C to +100°C, CL = 50 pF.

6. WS = number of wait states (measured in clock cycles, number of TC).

7. Use the expression to compute a maximum value.

RESET

All Pins

A[0–17]

9

8

Reset Value

Figure 2-3. Reset Timing

VIH

10

First Fetch

DSP56321 Technical Data, Rev. 11

2-8

Freescale Semiconductor

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