DSP56321 View Datasheet(PDF) - Freescale Semiconductor
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DSP56321 Datasheet PDF : 84 Pages
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AC Electrical Characteristics
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing5 (CONTINUED)
No.
Characteristics
Expression
200 MHz
Min Max
220 MHz
Min Max
240 MHz
Min Max
275 MHz
Unit
Min Max
20 Delay from RD assertion to interrupt
request deassertion for level sensitive
fast interrupts1, 6, 7
(WS + 3.25) × TC –
10.94
— Note 7 — Note 7 — Note 7 — Note 7 ns
21 Delay from WR assertion to interrupt
request deassertion for level sensitive
fast interrupts1, 6, 7
• SRAM WS = 3
• SRAM WS ≥ 4
(WS + 3) × TC – 10.94 — Note 7 — Note 7 — Note 7 — Note 7 ns
(WS + 2.5) × TC – 10.94 — Note 7 — Note 7 — Note 7 — Note 7 ns
24 Duration for IRQA assertion to recover
from Stop state
8.0 — 8.0 — 8.0 — 8.0 — ns
25 Delay from IRQA assertion to fetch of
first instruction (when exiting Stop)2, 3
• DPLL is not active during Stop
DPLT + (128K × TC) 662.2 209.9 662.2 209.9 662.2 209.9 662.2 209.9 —
(PCTL Bit 1 = 0) and Stop delay is
µs ms µs ms µs ms µs ms
enabled (Operating Mode Register
Bit 6 = 0)
• DPLL is not active during Stop
DPLT + (23.75 ± 0.5) × 6.9 188.8 6.9 188.8 6.9 188.8 6.9 188.8 µs
(PCTL Bit 1 = 0) and Stop delay is
TC
not enabled (Operating Mode
Register Bit 6 = 1)
• DPLL is active during Stop (PCTL
41.25 58.8 37.5 53.3 34.4 49.0 30.0 43.0 ns
Bit 1 = 1; Implies No Stop Delay)
(10.0 ± 1.75) × TC
26 Duration of level sensitive IRQA
assertion to ensure interrupt service
(when exiting Stop)2, 3
• DPLL is not active during Stop
DPLT + (128 K × TC) 805.4 — 805.4 — 805.4 — 805.4 — µs
(PCTL bit 1 = 0) and Stop delay is
enabled (Operating Mode Register
Bit 6 = 0)
• DPLL is not active during Stop DPLT + (20.5 ± 0.5) × TC 150.1 — 150.1 — 150.1 — 150.1 — µs
(PCTL bit 1 = 0) and Stop delay is
not enabled (Operating Mode
Register Bit 6 = 1)
• DPLL is active during Stop ((PCTL
bit 1 = 0; implies no Stop delay)
5.5 × TC
27.5 —
25
— 22.9 — 20.0 — ns
27 Interrupt Request Rate
• HI08, ESSI, SCI, Timer
• DMA
• IRQ, NMI (edge trigger)
• IRQ, NMI (level trigger)
28 DMA Request Rate
• Data read from HI08, ESSI, SCI
• Data write to HI08, ESSI, SCI
• Timer
• IRQ, NMI (edge trigger)
29 Delay from IRQA, IRQB, IRQC, IRQD,
NMI assertion to external memory
(DMA source) access address out
valid
12TC
8TC
8TC
12TC
6TC
7TC
2TC
3TC
4.25 × TC + 2.0
— 60.0 — 54.6 — 50.0 — 43.7 ns
— 40.0 — 36.4 — 33.4 — 29.2 ns
— 40.0 — 36.4 — 33.4 — 29.2 ns
— 60.0 — 54.6 — 50.0 — 43.7 ns
— 30.0 — 27.3 — 25.0 — 21.84 ns
— 35.0 — 31.9 — 29.2 — 25.48 ns
— 10.0 — 9.1 — 8.3 — 7.28 ns
— 15.0 — 13.7 — 12.5 — 10.92 ns
23.25 — 21.34 — 19.72 — 17.45 — ns
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
2-7
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