PC8240 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
PC8240 Datasheet PDF : 42 Pages
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Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation
25 MHz
40 ns
DLL will lock
DLL not guaranteed to lock
N=1
DLL_EXTEND = 1
33 MHz
30 ns
50 MHz
20 ns
100 MHz
10 ns
0 ns
N=1
DLL_EXTEND = 0
5 ns
10 ns
Tloop Propagation Delay Time in Nanoseconds
N=2
DLL_EXTEND = 1
N=2
DLL_EXTEND = 0
15 ns
Input AC Timing
Specifications
Table 10 provides the input AC timing specifications. See Figure 10 on page 21 and Fig-
ure 11 on page 21.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V ± 5%
and LVdd = 3.3V ± 5%
Table 10. Input AC Timing Specifications
Num
10a
10b1
10b2
10c
10d
10e
11a
11b
Characteristics
PCI Input Signals Valid to PCI_SYNC_IN (Input Setup)
Memory Control and Data Input Signals in Flow Through Mode Valid to
SDRAM_SYNC_IN (Input Setup)
Memory Control and Data Input Signals in Registered Mode Valid to
SDRAM_SYNC_IN (Input Setup)
Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
Two-wire Interface Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
Mode select Inputs Valid to HRST_CPU/HRST_CTRL (Input Setup)
PCI_SYNC_IN (SDRAM_SYNC_IN) to Inputs Invalid (Input Hold)
HRST_CPU/HRST_CTRL to Mode select Inputs Invalid (Input Hold)
Min
2.0
4.0
TBD
TBD
TBD
9*tCLK
1.0
TBD
Max
–
–
–
–
–
–
–
–
Unit
ns
ns
Notes
(2)(3)
(1)(3)
ns
(1)(3)
ns
(1)(3)
ns
(1)(3)
ns
(1)(3)(5)
ns
(1)(2)(3)
ns
(1)(3)(5)
Notes:
1. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the signal in
question to the VM = 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same
as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on
every rising and falling edge of PCI_SYNC_IN). See Figure 10 on page 21.
20 PC8240
2149A–HIREL–05/02
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