CDP1805AC View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

CDP1805AC

CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer

Intersil 

CDP1805AC, CDP1806AC

Interrupt Servicing

Register R(1) is always used as the program counter when-

ever interrupt servicing is initialized. When an interrupt

request occurs and the interrupt is allowed by the program

(again, nothing takes place until the completion of the cur-

rent instruction), the contents of the X and P registers are

stored in the temporary Register T, and X and P are set to

new values; hex digit 2 in X and hex digit 1 in P. Master Inter-

rupt Enable is automatically deactivated to inhibit further

interrupts. The user’s interrupt routine is now in control; the

contents of T may be saved by means of a single SAV

instruction (78) in the memory location pointed to by R(X) or

the contents of T, D, and DF may be saved using a single

DSAV instruction (6876). At the conclusion of the interrupt,

the user's routine may restore the pre-interrupted value of X

and P with either a RET instruction (70) which permits fur-

ther interrupts, or a DlS instruction (71), which disables fur-

ther interrupts.

Interrupt Generation and Arbitration (See Figure 6)

Interrupt requests can be generated from the following

sources:

1. Externally through the interrupt input (request not

latched).

2. Internally due to Counter/Timer response (request is

latched).

a. On the transition from count (01)16 to its next value

(counter underflow).

b. On the transition of EF1 in pulse measurement

mode 1.

c. On the transition of EF2 in pulse measurement

mode 2.

For an interrupt to be serviced by the CPU, the appropriate

Interrupt Enable flip-flops must be set. Thus, the External

Interrupt Enable flip-flop must be set to service an external

interrupt request, and the Counter Interrupt Enable flip-flop

must be set to service an internal Counter/Timer interrupt

request. In addition, the Master interrupt Enable flip-flop (as

used in the CDP1802) must be set to service either type of

request. All 3 flip-flops are initially enabled with the applica-

tion of a hardware reset, and, can be selectively enabled or

disabled with software: ClE, ClD instructions for the ClE flip-

flop; XlE, XlD instructions for the XIE flip-flop; RET, DIS

instructions for the MIE flip flop.

Short branch instructions on Counter Interrupt (BCI) and

External Interrupt (BXl) can be placed in the user's interrupt

service routine to provide a means of identifying and priori-

tizing the interrupt source. Note, however, that since the

External Interrupt request is not latched, it must remain

active until the short branch is executed if this priority arbitra-

tion scheme is used.

Interrupt requests can also be polled if automatic interrupt

service is not desired (MlE = 0). With the Counter Interrupt

and External Interrupt short branch instructions, the branch

will be taken if an interrupt request is pending, regardless of

the state of any of the 3 Interrupt Enable flip-flops. The

latched counter interrupt request signal will be reset when

the branch is taken, when the CPU is reset, or with a LDC

instruction with the Counter stopped. Note, that exiting a

counter-initiated interrupt routine without resetting the

counter-interrupt latch will result in immediately reentering

the interrupt routine.

Counter/Timer and Controls (See Figure 7)

This logic consists of a presettable 8-Bit down-counter (Mod-

ulo N type), and a conditional divide-by-32 prescaler. After

counting down to (01)16the counter returns to its initial value

at the next count and sets the Counter Interrupt Latch. It will

continue decrementing on subsequent counts. If the counter

is preset to (00)16 full 256 counts will occur.

During a Load Counter instruction (LDC) if the counter was

stopped with a STPC Instruction, the counter and its holding

register (CH) are loaded with the value in the D Register and

any previous counter interrupt is cleared. If the LDC is exe-

cuted when the counter is running, the contents of the D

Register are loaded into the holding register (CH) only and

any previous counter interrupt is not cleared. (LDC RESETS

the Counter Interrupt Latch only when the Counter is

stopped). After counting down to (01)16 the next count will

load the new initial value into the counter, set the Counter

Interrupt Latch, and operation will continue.

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