CDP1805AC View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

CDP1805AC

CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer

Intersil 

CDP1805AC, CDP1806AC

State Transitions

The CDP1805A and CDP1806A state transitions are shown which requires 9 clock pulses. Reset is asynchronous and

in Figure 13. Each machine cycle requires the same period can be forced at any time.

of time, 8 clock pulses, except the initialization cycle (INlT)

ENTER RESUME

PAUSE RUN

ENTER RESUME

PAUSE RUN

CLOCK

TPA

WAIT

PAUSE

70 71 00 01

tPLH

10 11 20 21 30

PAUSE

tPHL

CLOCK

TPB

PAUSE

50 51 60

PAUSE

61 70 71 00 01 10

tPLH

tPHL

WAIT

tSU

tSU tH

NOTE:

tSU

tSU tH

9. Pause (in clock waveform) while represented here as one clock

cycle in duration, could be infinitely long.

FIGURE 12A. TPA PAUSE TIMING

FIGURE 12B. TPB PAUSE TIMING

FIGURE 12. PAUSE MODE TIMING WAVEFORMS

RESET

PAUSE

INT • DMA • RESET

S1 RESET

DMA + INT

DMA • FORCE S1

S1 INIT

DMA

DMA

DMA

S2 DMA

IDLE • DMA • INT

FORCE S1

(LONG BRANCH,

LONG SKIP, NOP, RSXD, ETC)

S1 EXECUTE

DMA • IDLE • INT

• FORCE S1

FORCE S0

SO FETCH

DMA

INT • DMA • FORCE S1

S3 INT

PRIORITY:

RESET

FORCE S0, S1

DMA IN

DMA OUT

INT

DMA • INT

“68”

FORCE S0

DMA

INT • DMA

FIGURE 13. STATE TRANSITION DIAGRAM

16

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