CDP1805AC View Datasheet(PDF) - Intersil
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CDP1805AC Datasheet PDF : 30 Pages
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CDP1805AC, CDP1806AC
16. The short-branch instructions are two or three bytes long. The first byte specifies the condition to be tested, and the second specifies the
branching address, except for the branches on interrupt. For those, the first two bytes specify the condition to be tested and the third byte
specifies the branching address.
The short branch instruction can:
a. Branch unconditionally
b. Test for D = 0 or D ≠ 0
c. Test for DF = 0 or DF = 1
d. Test for Q = 0 or Q = 1
e. Test the status (1 or 0) of the four EF flags
f. Effect an unconditional no branch
g. Test for counter or external interrupts (BCI, BXI)
If the tested condition is met, then branching takes place; the branching address byte is loaded into the low-order byte position of the
current program counter. This effects a branch within the current 256-byte page of the memory, i.e., the page which holds the branching
address. If the tested condition is not met, the branching address byte is skipped over, and the next instruction in sequence is fetched
and executed. This same action is taken in the case of unconditional no branch (NBR).
17. The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP) and eight Long-Skip instructions.
The Unconditional Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute). Its action is to skip over the byte following it.
Then the next instruction in sequence is fetched and executed. This SKP instruction is identical to the unconditional No-Branch Instruc-
tion (NBR) except that the skipped-over byte is not considered part of the program.
The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute).
They can:
a. Skip unconditionally
b. Test for D = 0 or D ≠ 0
c. Test for DF = 0 or DF = 1
d. Test for Q = 0 or Q = 1
e. Test for MIE = 1
If the tested condition is met, then Long Skip takes place; the current program counter is incremented twice. Thus, two bytes are
skipped over and the next instruction in sequence is fetched and executed. If the tested condition is not met, then no action is taken.
Execution is continued by fetching the next instruction in sequence.
18. Instruction 6800 through 68FF take a minimum of 3 machine cycles and up to a maximum of 10 machine cycles. In all cases, the first two
cycles are fetches and subsequent cycles are executes. The first byte (68) of these two-byte op codes is used to generate the second
fetch, the second byte is then interpreted differently than the same code without the 68 prefix. DMA and INT requests are not serviced
until the end of the last execute cycle.
19. Arithmetic Operations:
The arithmetic and shift operations are the only instructions that can alter the content of DF. The syntax ‘(NOT DF)’ denotes the subtrac-
tion of the borrow.
Binary Operations:
After an ADD instruction
DF = 1 denotes a carry has occurred. Result is greater than FF16.
DF = 0 denotes a carry has not occurred.
After a SUBTRACT instruction
DF = 1 denotes no borrow. D is a true positive number.
DF = 0 denotes a borrow. D is in two's complement form.
Binary Coded Decimal Operations:
After a BCD ADD instruction
DF = 1 denotes a carry has occurred. Result is greater than 9910.
DF = 0 denotes a carry has not occurred.
After a BCD SUBTRACT instruction
DF = 1 denotes no borrow. D is a true positive decimal number.
Example
99
D
-88
M(R(X))
11
D
DF = 1
DF = 0 denotes a borrow. D is in ten's complement form.
Example
88
D
-99
M(R(X))
89
D
DF = 0
89 is the ten's complement of 11, which is the correct answer (with a minus value denoted by DF = 0).
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