CDP1805AC View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

CDP1805AC

CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer

Intersil 

CDP1805AC, CDP1806AC

INSTRUCTION SUMMARY

N

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

IDL

LDN

1

INC

2

DEC

3

BR BQ BZ BDF B1 B2 B3 B4 SKP BNQ BNZ BNF BN1 BN2 BN3 BN4

4

LDA

5

STR

6 IRX

OUT

†

INP

7 RET DIS LDXA STXD ADC SDB SHRC SMB SAV MARK REQ SEQ ADCI SDBI SHLC SMBI

8

GLO

9

GHI

A

PLO

B

PHI

C LBR LBQ LBZ LBDF NOP LSNQ LSNZ LSNF LSKP LBNQ LBNZ LBNF LSIE LSQ LSZ LSDF

D

SEP

E

SEX

F LDX OR AND XOR ADD SD SHR SM LDI ORI ANI XRI ADI SDI SHL SMI

‘68’ LINKED OPCODES (DOUBLE FETCH)

0 STPC DTC SPM2 SCM2 SPM1 SCM1 LDC STM GEC ETQ XIE XID CIE CID

-

-

2

DBNZ

3

-

-

-

-

-

-

-

-

-

-

-

-

-

-

BCI BXI

6

RLXA

7

-

-

-

- DADC - DSAV DSMB -

-

-

- DACI -

- DSBI

8

SCAL

9

SRET

A

RSXD

B

RNX

C

RLDI

F

-

-

-

- DADD -

- DSM -

-

-

- DADI -

- DSMI

†‘68’ is used as a linking OPCODE for the double fetch instructions.

29

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