RM7000-250T View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

RM7000-250T

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released

PMC-Sierra 

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet

Released

Since the performance counter can be set up to count clock cycles, it can be used as either a) a

second timer or b) a watchdog interrupt. A watchdog interrupt can be used as an aid in debugging

system or software “hangs.” Typically the software is setup to periodically update the count so that

no interrupt will occur. When a hang occurs the interrupt ultimately triggers thereby breaking free

from the hang-up.

4.35 Interrupt Handling

In order to provide better real time interrupt handling, the RM7000 provides an extended set of

hardware interrupts each of which can be separately prioritized and separately vectored.

In addition to the six external interrupt pins available on the R4000 and R5000 family processors,

the RM7000 provides four more interrupt pins for a total of ten external interrupts.

As described above, the performance counter is also a hardware interrupt source, INT[13]. Also,

whereas the R4000 and R5000 family processors map the timer interrupt onto INT[7], the

RM7000 provides a separate interrupt, INT[12], for this purpose freeing INT[7] for use as a pure

external interrupt.

All of these interrupts, INT[13..0], the Performance Counter, and the Timer, have corresponding

interrupt mask bits, IM[13..0], and interrupt pending bits, IP[13..0], in the Status, Interrupt

Control, and Cause registers. The bit assignments for the Interrupt Control and Cause registers are

shown in Table 11 and Table 12. The Status register has not changed from the RM5200 Family and

R5000, and is not shown.

The IV bit in the Cause register is the global enable bit for the enhanced interrupt features. If this

bit is clear then interrupt operation is compatible with the RM5200 Family and R5000. Although

not related to the interrupt mechanism, note that the W1 and W2 bits indicate which Watch register

caused a particular Watch exception.

In the Interrupt Control register, the interrupt vector spacing is controlled by the Spacing field as

described below. The Interrupt Mask field (IM[15..8]) contains the interrupt mask for interrupts

eight through thirteen. IM[15..14] are reserved for future use. The Timer Exclusive (TE) bit if set

moves the Timer interrupt to INT[12]. If clear, the Timer interrupt will be or’ed into INT[7] as on

the R5000.

The Interrupt Control register uses IM13 to enable the Performance Counter Control.

Priority of the interrupts is set via two new coprocessor 0 registers called Interrupt Priority Level

Lo (IPLLO) and Interrupt Priority Level Hi (IPLHI).

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

35

Document ID: PMC-2002175, Issue 1

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