RM7000-250T View Datasheet(PDF) - PMC-Sierra
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RM7000-250T Datasheet PDF : 54 Pages
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RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 9 Watch Control Register
Register Bit Field/Function
63 62 61 60:36 35:2 1:0
Watch1, 2 Store Load Instr 0
Addr 0
31:2
1
0
Watch Mask Mask
Mask Mask
Watch Watch
2
1
4.34 Performance Counters
Like the Test/Break-point capability described above, the Performance Counter feature has been
added to improve the observability and controllability of the processor thereby easing system
debug and, especially in the case of the performance counters, easing system tuning.
The Performance Counter feature is implemented using two new CP0 registers, PerfCount and
PerfControl. The PerfCount register is a 32-bit writable counter which causes an interrupt when bit
31 is set. The PerfControl register is a 32-bit register containing a five bit field which selects one
of twenty-two event types as well as a handful of bits which control the overall counting function.
Note that only one event type can be counted at a time and that counting can occur for user code,
kernel code, or both. The event types and control bits are listed in Table 10.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
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Document ID: PMC-2002175, Issue 1
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