RM7000-250T View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

RM7000-250T

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released

PMC-Sierra 

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet

Released

Pin Name Type

SysADC(7:0) Input/Output

SysCmd(8:0) Input/Output

SysCmdP

Input/Output

Description

System address/data check bus

An 8-bit bus containing parity check bits for the SysAD bus during data

cycles.

System command/data identifier bus

A 9-bit bus for command and data identifier transmission between the

processor and an external agent.

System Command/Data Identifier Bus Parity

For the RM7000, unused on input and zero on output.

Table 18 Clock/control interface Pins

Pin Name Type

Description

SysClock

Input

System clock

Master clock input used as the system interface reference clock. All

output timings are relative to this input clock. Pipeline operation

frequency is derived by multiplying this clock up by the factor selected

during boot initialization

VccP

Input

Vcc for PLL

Quiet VccInt for the internal phase locked loop. Must be connected to

VccInt through a filter circuit.

VssP

Input

Vss for PLL

Quiet Vss for the internal phase locked loop. Must be connected to

VssInt through a filter circuit.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

40

Document ID: PMC-2002175, Issue 1

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