S25FL256SDSBFIQ01 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDSBFIQ01

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

3. Signal Protocols

3.1 SPI Clock Modes

3.1.1

Single Data Rate (SDR)

The S25FL128S and S25FL256S devices can be driven by an embedded microcontroller (bus master) in either of the two following

clocking modes.

Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0

Mode 3 with CPOL = 1 and, CPHA = 1

For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the output data is

always available from the falling edge of the SCK clock signal.

The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring any data.

SCK will stay at logic low state with CPOL = 0, CPHA = 0

SCK will stay at logic high state with CPOL = 1, CPHA = 1

Figure 3.1 SPI SDR Modes Supported

CPOL=0_CPHA=0_SCK

CPOL=1_CPHA=1_SCK

CS#

SI

MSB

SO

MSB

Timing diagrams throughout the remainder of the document are generally shown as both mode 0 and 3 by showing SCK as both

high and low at the fall of CS#. In some cases a timing diagram may show only mode 0 with SCK low at the fall of CS#. In such a

case, mode 3 timing simply means clock is high at the fall of CS# so no SCK rising edge set up or hold time to the falling edge of

CS# is needed for mode 3.

SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In mode 0 the beginning of the

first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of SCK because SCK is already low

at the beginning of a command.

3.1.2

Double Data Rate (DDR)

Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are always latched on the rising

edge of clock, the same as in SDR commands. However, the address and input data that follow the instruction are latched on both

the rising and falling edges of SCK. The first address bit is latched on the first rising edge of SCK following the falling edge at the end

of the last instruction bit. The first bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle.

SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the next falling edge of

SCK. In mode 0 the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge

of SCK because SCK is already low at the beginning of a command.

CPOL=0_CPHA=0_SCK

CPOL=1_CPHA=1_SCK

CS#

Transfer_Phase

SI

SO

Figure 3.2 SPI DDR Modes Supported

Instruction

Inst. 7

Address

Inst. 0

A31 A30

Mode

A0 M7 M6

Dummy / DLP

M0

DLP7

Read Data

DLP0 D0 D1

Document Number: 001-98283 Rev. *I

Page 14 of 144

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