S25FL256SDSBFIQ01 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDSBFIQ01

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

3.3 Interface States

This section describes the input and output signal levels as related to the SPI interface behavior.

Table 3.1 Interface States Summary

Interface State

Power-Off

Low Power

Hardware Data Protection

Power-On (Cold) Reset

Hardware (Warm) Reset

Interface Standby

Instruction Cycle

Hold Cycle

Single Input Cycle

Host to Memory Transfer

Single Latency (Dummy) Cycle

Single Output Cycle

Memory to Host Transfer

Dual Input Cycle

Host to Memory Transfer

Dual Latency (Dummy) Cycle

Dual Output Cycle

Memory to Host Transfer

QPP Address Input Cycle

Host to Memory Transfer

Quad Input Cycle

Host to Memory Transfer

Quad Latency (Dummy) Cycle

Quad Output Cycle

Memory to Host Transfer

DDR Single Input Cycle

Host to Memory Transfer

DDR Dual Input Cycle

Host to Memory Transfer

DDR Quad Input Cycle

Host to Memory Transfer

DDR Latency (Dummy) Cycle

DDR Single Output Cycle

Memory to Host Transfer

DDR Dual Output Cycle

Memory to Host Transfer

DDR Quad Output Cycle

Memory to Host Transfer

Legend

Z = no driver - floating signal

HL = Host driving VIL

HH = Host driving VIH

HV = either HL or HH

X = HL or HH or Z

HT = toggling between HL and HH

ML = Memory driving VIL

MH = Memory driving VIH

MV = either ML or MH

VCC

< VCC (low)

< VCC (cut-off)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

≥ VCC (min)

VIO

 VCC

 VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ V≤IOV(CmCin)

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ V≤IOV(CmCin)

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ VIO (min)

≤ VCC

≥ V≤IOV(CmCin)

≥ VIO (min)

≤ VCC

RESET#

X

X

X

HL

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

HH

SCK

CS#

X

X

X

X

X

X

X

X

X

HH

HT

HL

HV or HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HT

HL

HOLD# /

IO3

X

X

WP# /

IO2

X

X

SO /

IO1

Z

SI / IO0

X

Z

X

X

X

Z

X

X

X

Z

X

X

X

Z

X

HH

HV

Z

HV

HL

X

X

X

HH

X

Z

HV

HH

X

Z

X

HH

X

MV

X

HH

X

HV

HV

HH

X

X

X

HH

X

MV

MV

X

X

X

HV

HV

HV

HV

HV

X

X

X

X

MV

MV

MV

MV

X

X

X

HV

X

X

HV

HV

HV

MV or Z

Z

HV

HV

HV

MV or Z

MV or

Z

MV or Z

Z

MV

X

Z

Z

MV

MV

MV

MV

MV

MV

Document Number: 001-98283 Rev. *I

Page 19 of 144

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