S25FL256SDSBFIQ01 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDSBFIQ01

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

3.2 Command Protocol

All communication between the host system and S25FL128S and S25FL256S memory devices is in the form of units called

commands.

All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands

may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All

instruction, address, and data information is transferred serially between the host system and memory device.

All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.

Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to the host serially on

the SO signal.

Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be returned to the host as a

sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four bit (nibble)

groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0,

IO1, IO2, and IO3.

Commands are structured as follows:

Each command begins with CS# going low and ends with CS# returning high. The memory device is selected by the host

driving the Chip Select (CS#) signal low throughout a command.

The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.

Each command begins with an eight bit (byte) instruction. The instruction is always presented only as a single bit serial

sequence on the Serial Input (SI) signal with one bit transferred to the memory device on each SCK rising edge. The

instruction selects the type of information transfer or device operation to be performed.

The instruction may be stand alone or may be followed by address bits to select a location within one of several address

spaces in the device. The instruction determines the address space used. The address may be either a 24-bit or a 32-bit

byte boundary, address. The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in

DDR commands.

The width of all transfers following the instruction are determined by the instruction sent. Following transfers may continue to

be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit groups per (dual) transfer on

the IO0 and IO1 signals, or they may be done in 4 bit groups per (quad) transfer on the IO0-IO3 signals. Within the dual or

quad groups the least significant bit is on IO0. More significant bits are placed in significance order on each higher

numbered IO signal. SIngle bits or parallel bit groups are transferred in most to least significant bit order.

Some instructions send an instruction modifier called mode bits, following the address, to indicate that the next command will

be of the same type with an implied, rather than an explicit, instruction. The next command thus does not provide an

instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same

command type is repeated in a sequence of commands. The mode bit transfers occur on SCK rising edge, in SDR

commands, or on every SCK edge, in DDR commands.

The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before

read data is returned to the host.

Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.

SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles (also referred

to as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from the outputs on SCK

falling edge at the end of the last read latency cycle. The first read data bits are considered transferred to the host on the

following SCK rising edge. Each following transfer occurs on the next SCK rising edge, in SDR commands, or on every

SCK edge, in DDR commands.

If the command returns read data to the host, the device continues sending data transfers until the host takes the CS# signal

high. The CS# signal can be driven high after any transfer in the read data sequence. This will terminate the command.

Document Number: 001-98283 Rev. *I

Page 15 of 144

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