HMP8154 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
HMP8154 Datasheet PDF : 34 Pages
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HMP8154, HMP8156A
CLOSED
CAPTIONING
ENABLE BITS
00
01
10
11
TABLE 8. CLOSED CAPTIONING MODES
CAPTIONING REGISTER
284A
21A
OUTPUT LINE(S)
284B
21B
None
Ignored
Ignored
21 (NTSC)
18 (M PAL)
22 (Other PAL)
Ignored
Caption Data
284 (NTSC)
281 (M PAL)
335 (Other PAL)
Caption Data
Ignored
21, 284 (NTSC)
18, 281 (M PAL)
22, 335 (Other PAL)
Caption Data
Caption Data
WRITE STATUS BIT
284
Always 1
Always 1
21
Always 1
0 = Loaded
1 = Output
0 = Loaded
1 = Output
Always 1
0 = Loaded
1 = Output
0 = Loaded
1 = Output
Analog Outputs
The HMP8154/HMP8156A converts the video data into
analog signals using four 10-bit DACs running at the CLK2
rate. The DACs output a current proportional to the digital
data. The full scale output current is determined by the
reference voltage VREF and an external resistor RSET. The
full scale output current is given by:
IFULLSCALE (mA) = 3.9 * VREF (V)/RSET (k)
(EQ 1.)
VREF must be chosen such that it is within the part’s
operating range; RSET must be chosen such that the
maximum output current is not exceeded.
If the VREF pin is not connected, the HMP8154/HMP8156A
provides an internal reference voltage. Otherwise, the
applied voltage overdrives the internal reference. If an
external reference is used, it must decoupled from any
power supply noise. An example external reference circuit is
shown in the Applications section.
The HMP8154/HMP8156A generates 1VP-P nominal video
signals across 37.5 loads corresponding to doubly
terminated 75 lines. The encoder may also drive larger
loads. The full scale output current and load must be chosen
such that the maximum output voltage is not exceeded.
Output DAC Filtering
Since the DACs run at 2X the pixel sample rate, the sin(x)/x
rolloff of the outputs is greatly reduced, and there are fewer
high frequency artifacts in the output spectrum. This allows
using simple analog output filters. The analog output filter
should be flat to Fs/4 and have good rejection at 3Fs/4.
Example filters are shown in the Applications section.
Composite + Y/C Output Mode
The HMP8154/HMP8156A provides three output modes:
S-video, RGB, and power down. When S-video outputs are
selected, the encoder outputs the luminance, modulated
chrominance, and two copies of the composite video signals.
All four outputs are time aligned.
Composite + RGB Output Mode
When analog RGB video is selected, the
HMP8154/HMP8156A transforms the filtered 8:8:8 YCbCr
data into 8:8:8 RGB data. The transform matrix uses
different coefficients to generate NTSC or PAL video levels.
The analog RGB outputs have a range of 0.3-1.0V with an
optional blanking pedestal. Composite sync information (0.0-
0.3V) may be optionally added to the green output. Closed
captioning data is not included on the RGB outputs. The
HMP8154/HMP8156A also generates composite video
when in RGB output mode. All four outputs are time aligned.
The HMP8154/HMP8156A provides selectable pin outs for
the RGB outputs. When the SCART compatibility bit is
cleared, the analog composite video is output onto the
NTSC/PAL 1 pin. Red information is output onto the
NTSC/PAL 2 pin, blue information is output onto the C pin,
and green information is output onto the Y pin.
When the bit is set, the analog composite video is output
onto the Y pin. Red information is output onto the C pin, blue
video is output on the NTSC/PAL 2 pin, and the green signal
is output on the NTSC/PAL 1 pin. The output pin
assignments are summarized in Table 9.
TABLE 9. OUTPUT PIN ASSIGNMENTS
OUTPUT MODE
(SCART SELECT BIT)
PIN NAME
COMP. WITH
PIN
Y/C
#
(X)
COMP. W/
RGB
(0)
COMP. W/
RGB
(1)
Y
3
Luma
Green
Composite
C
7
Chroma
Blue
Red
NTSC/PAL 1 11 Composite Composite
Green
NTSC/PAL 2 15 Composite
Red
Blue
Power Down Modes
To reduce power dissipation, any of the four output DACs
may be turned off. Each DAC has an independent enable bit.
Each output may be disabled in the host control register.
When the power down mode is enabled, all of the DACs and
internal voltage reference are powered down (forcing their
outputs to zero) and the data pipeline registers are disabled.
FN4343 Rev.5.00
August 20, 2009
Page 16 of 34
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