LH28F008SC View Datasheet(PDF) - Sharp Electronics
Part Name
Description
Manufacturer
LH28F008SC Datasheet PDF : 38 Pages
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LH28F008SC
8M (1M × 8) Flash Memory
START
WRITE 20H
BLOCK ADDRESS
WRITE D0H
BLOCK ADDRESS
READ STATUS
REGISTER
SR.7 = 0
1
NO SUSPEND BLOCK
ERASE LOOP
SUSPEND YES
BLOCK
ERASE?
FULL STATUS
CHECK IF DESIRED
BLOCK ERASE
COMPLETED
BUS
OPERATION
COMMAND
COMMENTS
Write
Write
Read
Standby
Erase
Setup
Erase
Confirm
Data = 20H
Addr = Within block to be
erased
Data = D0H
Addr = Within block to be
erased
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or
after a sequence of block erasures.
Write FFH after the last operation to place
device in read array mode.
FULL STATUS CHECK PROCEDURE
STATUS REGISTER
DATA
(see above)
SR.3 = 1
0
SR.1 = 1
0
SR.4, 5 = 1
0
VPP RANGE
ERROR
DEVICE
PROTECT
ERROR
COMMAND
SEQUENCE
ERROR
SR.5 = 1
BLOCK ERASE
ERROR
BUS
OPERATION
Standby
Standby
Standby
Standby
COMMAND
COMMENTS
Check SR.3
1 = VPP Low Detect
Check SR.1
1 = Device Protect Detect
RP = VIH Block Lock-Bit is Set
Only required for systems
implemening lock-bit
configuration
Check SR.4, 5
Both 1 = Command Sequence
Error
Check SR.5
1 = Block Erase Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0
BLOCK ERASE
SUCCESSFUL
Figure 6. Automated Block Erase Flowchart
28F008SC-6
14
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