LH28F008SC View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F008SC

8M (1M × 8) Flash Memory

Sharp Electronics 

LH28F008SC

8M (1M × 8) Flash Memory

DESIGN CONSIDERATIONS

Three-Line Output Control

The device will often be used in large memory

arrays. SHARP provides three control inputs to accom-

modate multiple memory connections. Three-line

control provides for:

• Lowest possible memory power dissipation

• Complete assurance that data bus contention will

not occur.

To use these control input efficiently, an address

decoder should enable CE» while OE» should be connected

to all memory devices and the system’s READ control line.

This assures that only selected memory devices have ac-

tive outputs while deselected memory devices are in

standby mode. RP» should be connected to the system

POWERGOOD signal to prevent unintended writes dur-

ing system power transitions. POWERGOOD should also

toggle during system reset.

RY /» BY » and Block Erase, Byte Write, and

Lock-Bit Configuration Polling

RY »/BY » is a full CMOS output that provides a hard-

ware method of detecting block erase, byte write and

block-bit configuration completion. It transitions low af-

ter lock erase, byte write, or lock-bit configuration com-

mands and returns to VOH when the WSM has finished

executing the internal algorithm.

RY »/BY » can be connected to an interrupt input of the

system CPU or controller. It is active at all times.

RY »/BY » is also VOH when the device is in block erase

suspend (with byte write inactive), byte write suspend

or deep power-down modes.

Power Supply Decoupling

Flash memory power switching characteristics

require careful device decoupling. System designers are

interested in three supply current issues; standby cur-

rent levels, active current levels and transient peaks pro-

duced by falling and rising edges of CE » and OE ».

Transient current magnitudes depend on the device out-

puts’ capacitive and inductive loading. Two-line control

and proper decoupling capacitor selection will suppress

transient voltage peaks. Each device should have a

0.1 µF ceramic capacitor connected between its VCC

and GND and between its VPP and GND. These high-

frequency, low inductance capacitors should be placed

as close as possible to package leads. Additionally, for

every eight devices, a 4.7 µF electrolytic capacitor

should be placed at the array’s power supply connec-

tion betweenVCC and GND.The bulk capacitor will over-

come voltage slumps caused by PC board trace

inductance.

VPP Trace on Printed Circuit Boards

Updating flash memories that reside in the target

system requires that the printed circuit board designer

pay attention to the VPP Power supply trace. The VPP

pin supplies the memory cell current for byte writing and

block erasing. Use similar trace widths and layout con-

siderations given to the VCC power bus. Adequate VPP

supply traces and decoupling will decreaseVPP voltage

spikes and overshoots.

VCC, VPP, RP » Transitions

Block erase, byte write and lock-bit configuration are

not guaranteed if VPP falls outside of a valid VPPH1/2/3

range, VCC falls outside of a valid VCC1/2/3 range, or

RP » ≠ VIH or VHH. If VPP error is detected, status register

bit SR.3 is set to '1' along with SR.4 or SR.5,

depending on the attempted operation. If RP» transitions

to VIL during block erase, byte write, or lock-bit configu-

ration, RY »/BY » will remain low until the reset operation

is complete. Then, the opration will abort and the

device will enter deep power-down.The aborted opera-

tion may leave data partially altered.Therefore, the com-

mand sequence must be repeated after normal

operation is restored. Device power-off or RP» transiitions

to VIL clear the status register.

The CUI latches commands issued by system soft-

ware and is not altered by VPP or CE» transitions or WSM

actions. Its state is read array mode upon power-up,

after exit from deep power-down or afterVCC transitions

below VLKO.

After block erase, byte write, or lock-bit configura-

tion, even after VPP transitions down to VPPLK, the CUI

must be placed in read array mode via the Read Array

command if subsequent access to the memory array is

desired.

Power-Up/Down Protection

The device is designed to offer protection against

accidental block erasure, byte writing, or lock-bit con-

figuration during power transitions. Upon power-up, the

device is indifferent as to which power supply (VPP or

VCC) powers-up first. Internal circuitry resets the CUI to

read array mode at power-up.

A system designer must guard against spurious

writes for VCC voltages above VLKO when VPP is active.

Since both WE » and CE » must be low for a command

write, driving either to VIH will inhibit writes. The CUI’s

two-step command sequence archiecture provides

added level of protection against data alteration.

In-system block lock and unlock capability prevents

inadvertent data alteration.The device is disabled while

RP » = VIL regardless of its control inputs state.

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