OR4E10 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

OR4E10

ORCA® Series 4 Field-Programmable Gate Arrays

Agere -> LSI Corporation 

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Input/Output Cells

(continued)

The PIOs are located along the perimeter of the device.

The PIO name is represented by a two-letter designa-

tion to indicate on which side of the device it is located

followed by a number to indicate in which row or column

it is located. The first letter, P, designates that the cell is

a PIO and not a PLC. The second letter indicates the

side of the array where the PIO is located. The four

sides are left (L), right (R), top (T), and bottom (B). The

individual I/O pad is indicated by a single letter (either

A, B, C, or D) placed at the end of the PIO name. As an

example, PL10A indicates a pad located on the left side

of the array in the tenth row.

Each PIC interfaces to four bond pads and contains the

necessary routing resources to provide an interface

between I/O pads and the PLCs. Each PIC is com-

posed of four programmable I/Os and significant routing

resources. Each PIC contains input buffers, output buff-

ers, routing resources, latches/FFs, and logic and can

be configured as an input, output, or bidirectional

I/O. Any PIO is capable of supporting the I/O standard

listed in Table 12 and supporting DDR and ZBT specifi-

cations.

The I/O on the OR4Exxx Series devices allows compli-

ance with PCI Local Bus (Rev. 2.2) 3.3 V signaling

environments. The signaling environment used for

each input buffer can be selected on a per-pin basis.

The selection provides the appropriate I/O clamping

diodes for PCI compliance.

The CIBs that bound the PIOs have significant local

routing resources, similar to routing in the PLCs. This

new routing increases the ability to fix user pinouts

prior to placement and routing of a design and still

maintain routability. The flexibility provided by the rout-

ing also provides for increased signal speed due to a

greater variety of optimal signal paths.

Included in the PIO routing interface is a fast path from

the input pins to the PFU logic. This feature allows for

input signals to be very quickly processed by the SLIC

decoder function and used on-chip or sent back off of

the FPGA. Also, the Series 4 PIOs include latches and

FFs and options for using fast, dedicated secondary,

and edge clocks.

A diagram of a single PIO is shown in Figure 22, and

Table 15 provides an overview of the programmable

functions in an I/O cell.

OUTSH

OUTDDMUX

OUTDD

0

OUTFFMUX

OUTFF

0

CLK4MUX

EC

SC

CEMUX0

CE

1

LSRMUX

LSR

DEL0

DEL1

DEL2

DEL3

OUTPUT SIDE

LEVELMODE

LVTTL

RESISTOR

OFF

INPUT SIDE

AND

LVCMOS2

ON

LVCMOS18

OUTDD

CLK

OUTSH

CLK

OUTDD

OUTREG

OUTREG

DO

CK

SP

LSR

NAND

PCI

OR

NOR

XOR

XNOR

PLOGIC

BUFMODE

SLEW

FAST

NA

PMUX

OUTMUX

OUTSHMUX

SSTL2

SSTL3

HSTL1

HSTL3

GTL

GTLPLUS

PECL

LVPECL

MILLIAMPS

SIX

TWELVE

TWENTYFOUR

NA

KEEPERMODE

OFF

ON

LATCHFF

INCK

P2MUX

TSMUX

USRTS

LVDS

DELAY

CELL

IOPAD

INMUX

EC NORMAL

D0

D0

CK

D1

INFF

OUTDD

RESET

SET

LATCH

FF

TSREG 1

DO 0

CK

LSR

RESET

SET

PULLMODE

UP

DOWN

NONE

CE SC

1

CEMUXI

INVERTED

CK

DEL0

DEL1

DEL2

DEL3

SP

LATCHFF

LATCH

FF

LSR

RESET

SET INDDMUX

INDD

0

GSR

ENABLED

DISABLED

SRMODE

CE_OVER_LSR

LSR_OVER_CE

ASYNC

Figure 22. Series 4 PIO Image from ORCA Foundry

5-9732(F)

Lucent Technologies Inc.

33

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