OR4E10 View Datasheet(PDF) - Agere -> LSI Corporation
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OR4E10 Datasheet PDF : 124 Pages
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Preliminary Data Sheet
December 2000
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
Table 15. PIO Options
Input
Input Level
Input Speed
Float Value
Register Mode
Clock Sense
Input Selection
Keeper Mode
Option
LVTTL, LVCMOS 2,
LVCMOS 1.8, 3.3 V PCI Compliant.
Fast, Delayed.
Pull-up, Pull-down, None.
Latch, FF, Fast Zero Hold FF, None
(direct input).
Inverted, Noninverted.
Input 1, Input 2, Clock Input.
On, Off.
LVDS Resistor On, Off.
Output
Option
Output Drive 12 mA/6 mA or 6 mA/3 mA
Current
24 mA/12 mA.
Output Function Normal, Fast Open Drain.
Output Speed Fast, Slew.
Output Source FF Direct-out, General Routing.
Output Sense Active-high, Active-low.
3-State Sense Active-high, Active-low (3-state).
FF Clocking
Clock Sense
Logic Options
Edge Clock, System Clock.
Inverted, Noninverted.
See Table 17.
I/O Controls
Option
Clock Enable Active-high, Active-low, Always
Enabled.
Set/Reset Level Active-high, Active-low, No Local
Reset.
Set/Reset Type Synchronous, Asynchronous.
Set/Reset Priority CE over LSR, LSR over CE.
GSR Control Enable GSR, Disable GSR.
Outputs
The PIO’s output drivers for TTL/CMOS outputs have
programmable drive capability and slew rates. Two
propagation delays (fast, slewlim) are available on out-
put drivers. There are three combinations of program-
mable drive currents (24 mA sink/12 mA source, 12 mA
sink/6 mA, and 6 mA sink/3 mA source). At powerup,
the output drivers are in slewlim mode and
12 mA sink/6 mA source. If an output is not to be driven
in the selected configuration mode, it is 3-stated.
The output buffer signal can be inverted, and the
3-state control signal can be made active-high, active-
low, or always enabled. In addition, this 3-state signal
can be registered or nonregistered. Additionally, there
Lucent Technologies Inc.
is a fast, open-drain output option that directly connects
the output signal to the 3-state control, allowing the out-
put buffer to either drive to a logic 0 or 3-state, but
never to drive to a logic 1.
The PIO has both input and output shift register capa-
bilities. This ability allows the data rate to be reduced
from the pad or increased to the pad by two or four
times. The shift register block (SRB) is available in
groups of four PIO. Both the input and output shift reg-
isters are controlled by the same clock and can operate
at the same time at the same speed as long as the
SRB is not connected to the same pads.The output
control signals are similar to the input control signals in
that they are per pair of PIOs.
Bus Hold
Each PIO can be programmed with a KEEPERMODE
feature. This element is user programmed for bus hold
requirements. This mode retains the last known state of
a bus when the bus goes into 3-state. It prevents float-
ing buses and saves system power.
PIO Register Control Signals
The PIO latches/FFs have various clock, clock enable
(CE), local set/reset (LSR), and GSRN controls. Table
16 provides a summary of these control signals and
their effect on the PIO latches/FFs. Note that all control
signals are optionally invertible. The output control sig-
nals are similar to the input control signals in that they
are per pair of PIOs.
Table 16. PIO Register Control Signals
Control Signal
Effect/Functionality
Edge Clock
(ECLK)
Clocks input fast-capture latch;
optionally clocks output FF, or
3-state FF.
System Clock Clocks input latch/FF; optionally
(SCLK)
clocks output FF, or 3-state FF.
Clock Enable
(CE)
Optionally enables/disables input FF
(not available for input latch mode);
optionally enables/disables output
FF; separate CE inversion capability
for input and output.
Local Set/Reset Option to disable; affects input latch/
(LSR)
FF, output FF, and 3-state FF if
enabled.
Global Set/Reset Option to enable or disable per PIO
(GSRN)
(the input FF, output FF, and
3-state FF) after initial configuration.
Set/Reset Mode
The input latch/FF, output FF, and
3-state FF are individually set or
reset by both the LSR and GSRN
inputs.
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