OR4E10 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

OR4E10

ORCA® Series 4 Field-Programmable Gate Arrays

Agere -> LSI Corporation 

ORCA Series 4 FPGAs

Programmable Input/Output Cells (continued)

PIO

PIO

PIO

PIO

Preliminary Data Sheet

December 2000

SHIFT REGISTER SHIFT REGISTER

INTO FPGA

OUT FROM FPGA

CLK

Figure 24. PIO Shift Register

0204(F).

Special Function Blocks

Internal Oscillator

The internal oscillator resides in the upper left corner of

the FPGA array. It has output clock frequencies of

1.25 MHz and 10 MHz. The internal oscillator is the

source of the internal CCLK used for configuration. It

may also be used after configuration as a general-

purpose clock signal.

Global Set/Reset (GSRN)

The GSRN logic resides in the lower-right corner of the

FPGA. GSRN is an invertible (default active-low) signal

that is used to reset all of the user-accessible latches/

FFs on the device. GSRN is automatically asserted at

powerup and during configuration of the device.

The timing of the release of GSRN at the end of config-

uration can be programmed in the start-up logic

described below. Following configuration, GSRN may

be connected to the RESET pin via dedicated routing, or

it may be connected to any signal via normal routing.

Within each PFU and PIO, individual FFs and latches

38

can be programmed to either be set or reset when

GSRN is asserted. Series 4 allows individual PFUs and

PIOs to turn off the GSRN signal to its latches/FFs

after configuration.

The RESET input pad has a special relationship to

GSRN. During configuration, the RESET input pad

always initiates a configuration abort, as described in

the FPGA States of Operation section. After configura-

tion, the GSRN can either be disabled (the default),

directly connected to the RESET input pad, or sourced

by a lower-right corner signal. If the RESET input pad is

not used as a global reset after configuration, this pad

can be used as a normal input pad.

Start-Up Logic

The start-up logic block can be configured to coordi-

nate the relative timing of the release of GSRN, the

activation of all user I/Os, and the assertion of the

DONE signal at the end of configuration. If a start-up

clock is used to time these events, the start-up clock

can come from CCLK, or it can be routed into the start-

up block using lower-right corner routing resources.

Lucent Technologies Inc.

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