OR4E10 View Datasheet(PDF) - Agere -> LSI Corporation
Part Name
Description
Manufacturer
OR4E10 Datasheet PDF : 124 Pages
| |||
ORCA Series 4 FPGAs
Preliminary Data Sheet
December 2000
Special Function Blocks (continued)
D[7:0]
MICRO-
PROCESSOR
INTR
D[7:0]
TDO
LUCENT
BOUNDARY-
SCAN
MASTER
CE
TMS0
RA
TCK
R/W
DAV (BSM)
TDI
INT
SP
TDI
TDO
ORCA
SERIES
FPGA
TMS (DUT)
TCK
TDI
TDO
ORCA
SERIES
FPGA
TMS (DUT)
TCK
Figure 26. Boundary-Scan Interface
TDI
TDO
ORCA
SERIES
FPGA
TMS (DUT)
TCK
5-6765(F)
The boundary-scan support circuit shown in Figure 26
is the 497Aa boundary-scan master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general MPI and provides paral-
lel-to-serial/serial-to-parallel conversion, as well as
three 8K data buffers. The BSM also increases test
throughput with a dedicated automatic test-pattern
generator and with compression of the test response
with a signature analysis register. The PC-based
boundary-scan test card/software allows a user to
quickly prototype a boundary-scan test setup.
Boundary-Scan Instructions
The Series 4 boundary-scan circuitry includes ten
IEEE 1149.1, 1149.2, and 1532/D1 instructions and six
ORCA-defined instructions. These also include one
IEEE 1149.3 optional instruction. A 6-bit wide instruc-
tion register supports all the instructions listed in
Table 22. The BYPASS instruction passes data inter-
nally from TDI to TDO after being clocked by TCK.
Table 22. Boundary-Scan Instructions
Code
000000
000001
000011
000100
000101
000110
001000
001001
001010
001011
001101
001110
010001
010010
010011
010100
010101
111111
Instruction
EXTEST
SAMPLE
PRELOAD
RUNBIST
IDCODE
USERCODE
ISC_ENABLE
ISC_PROGRAM
ISC_NOOP
ISC_DISABLE
ISC_PROGRAM_USERCODE
ISC_READ
PLC_SCAN_RING1
PLC_SCAN_RING2
PLC_SCAN_RING3
RAM_WRITE
RAM_READ
BYPASS
40
Lucent Technologies Inc.
Share Link: 