OR4E10 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

OR4E10

ORCA® Series 4 Field-Programmable Gate Arrays

Agere -> LSI Corporation 

ORCA Series 4 FPGAs

Preliminary Data Sheet

December 2000

Programmable Input/Output Cells

(continued)

The PIO output FF can perform output data multiplex-

ing with no PLC resources required. This type of

scheme is necessary for DDR applications which

require data clocking out of the I/O on both edges of

the clock. In this scheme, the output of OUTFF and

OUTDD are serialized and shifted out on both the posi-

tive and negative edges of the clock using the shift reg-

isters.

The PIC logic block can also generate logic functions

based on the signals on the OUTDD and CLK ports of

the PIO. The functions are AND, NAND, OR, NOR,

XOR, and XNOR. Table 17 is provided as a summary

of the PIO logic options.

Table 18. Compatible Mixed I/O Standards

VDDIO BANK

Voltage

Compatible Standards

3.3 V

2.5 V

1.8 V

1.5 V

LVTTL, SSTL3-I, SSTL3-II, GTL, GTL+,

PECL

LVCMOS2, SSTL2-I, SSTL2-II, LVDS,

LVPECL

LVCMOS18

HSTL I, HSTL III, HSTL IV

TL

TC

TR

Table 17. PIO Logic Options

Option

AND

NAND

OR

NOR

XOR

XNOR

Description

Output logical AND of signals

on OUTFF and clock.

Output logical NAND of signals

on OUTFF and clock.

Output logical OR of signals on

OUTFF and clock.

Output logical NOR of signals

on OUTFF and clock.

Output logical XOR of signals

on OUTFF and clock.

Output logical XNOR of signals

on OUTFF and clock.

Flexible I/O features allow the user to select I/O to meet

different high-speed interface requirements. These I/Os

require different input references or supply voltages.

The perimeter of the device is divided into groups of

PIOs or buffer banks. For each bank, there is a sepa-

rate VDDIO. Every device is equally broken up into eight

I/O banks. The VDDIO supplies the correct output volt-

age for a particular standard. The user must supply the

appropriate power supply to the VDDIO pin. Within a

bank, several I/O standards may be mixed as long as

they use a common VDDIO. Also, some interface stan-

dards require a specified threshold voltage known as

VREF. In these modes, where a particular VREF is

required, the device is automatically programmed to

dedicate a pin for the appropriate VREF which must be

supplied by the user. The VREF is dedicated exclusively

to the bank and cannot be intermixed with other signal-

ing requiring other VREF voltages. However, pins not

requiring VREF can be mixed in the bank. The VREF pad

is then no longer available to the user for general use.

See Table 14 for a list of the I/O standards supported.

36

PLC ARRAY

BL

BC

BR

0205(F).

Figure 23. ORCA High-Speed I/O Banks

High-Speed Memory Interfaces

PIO features allow high-speed interfaces to external

SRAM and/or DRAM devices. Series 4 I/Os provide

200 MHz ZBT requirements when switching between

write and read cycles. ZBT allows 100% use of bus

cycles during back-to-back read/write and write/read

cycles. However, this maximum utilization of the bus

increases probability of bus contention when the inter-

faced devices attempt to drive the bus to opposite logic

values. The LVTTL I/O interfaces directly with commer-

cial ZBT SRAMs signaling and allows the versatility to

program the FPGA drive strengths from 6 mA to

24 mA.

DDR allows data to be read or written on both the rising

and the falling edge of the clock which delivers twice

the bandwidth. QDR (quad data rate) are similar, but

have separate read and write parts for over double the

bandwidth. The DDR capability in the PIO also allows

double the bandwidth per pin for generic transfer of

data between two devices. DDR doubles the memory

speed from SDRAMs without the need to increase

clock frequency. The flexibility of the PIO allows

133 MHz/266 Mbits per second performance using the

SSTL I/O features of the Series 4. All DDR interface

functions are built into the PIO.

Lucent Technologies Inc.

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