OR4E10 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

OR4E10

ORCA® Series 4 Field-Programmable Gate Arrays

Agere -> LSI Corporation 

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Special Function Blocks (continued)

Temperature Sensing

The built-in temperature-sensing diodes allow junction

temperature to be measured during device operation. A

physical pin (PTEMP) is dedicated for monitoring

device junction temperature. PTEMP works by forcing a

10 µA current in the forward direction, and then mea-

suring the resulting voltage. The voltage decreases

with increasing temperature at approximately

–1.69 mV/°C. A typical device with a 85 °C device tem-

perature will measure approximately 630 mV.

Table 21. Dedicated Temperature Sensing

Dedicated Temperature Sensing

Diode Pin Per Package

BA352

AB3

BC432

AH31

BM680

AK4

Boundary-Scan

The IEEE standards 1149.1 and 1149.2 (IEEE Stan-

dard test access port and boundary-scan architecture)

are implemented in the ORCA series of FPGAs. It

allows users to efficiently test the interconnection

between integrated circuits on a PCB as well as test the

integrated circuit itself. The IEEE 1149 standard is a

well-defined protocol that ensures interoperability

among boundary-scan (BSCAN) equipped devices

from different vendors.

Series 4 FPGAs are also compliant to IEEE standard

1532/D1. This standard for boundary-scan based in-

system configuration of programmable devices pro-

vides a standardized programming access and method-

ology for FPGAs. A device, or set of devices,

implementing this standard may be programmed, read

back, erased verified, singly or concurrently, with a

standard set of resources.

The IEEE 1149 standards define a test access port

(TAP) that consists of a four-pin interface with an

optional reset pin for boundary-scan testing of inte-

grated circuits in a system. The ORCA Series FPGA

provides four interface pins: test data in (TDI), test

mode select (TMS), test clock (TCK), and test data out

(TDO). The PRGM pin used to reconfigure the device

also resets the boundary-scan logic.

The user test host serially loads test commands and

test data into the FPGA through these pins to drive out-

puts and examine inputs. In the configuration shown in

Figure 26, where boundary-scan is used to test ICs,

test data is transmitted serially into TDI of the first

BSCAN device (U1), through TDO/TDI connections

Lucent Technologies Inc.

between BSCAN devices (U2 and U3), and out TDO of

the last BSCAN device (U4). In this configuration, the

TMS and TCK signals are routed to all boundary-scan

ICs in parallel so that all boundary-scan components

operate in the same state. In other configurations, mul-

tiple scan paths are used instead of a single ring. When

multiple scan paths are used, each ring is indepen-

dently controlled by its own TMS and TCK signals.

Figure 26 provides a system interface for components

used in the boundary-scan testing of PCBs. The three

major components shown are the test host, boundary-

scan support circuit, and the devices under test

(DUTs). The DUTs shown here are ORCA Series

FPGAs with dedicated boundary-scan circuitry. The

test host is normally one of the following: automatic test

equipment (ATE), a workstation, a PC, or a micropro-

cessor.

TMS TDI

TCK

TDO

U1

net a

net b

net c

S

TMS TDI

TCK

TDO

U2

TMS TDI

TCK

TDO

U3

TMS TDI

TCK

TDO

U4

TDI

TMS

TCK

TDO

SEE ENLARGED VIEW BELOW.

TDO TCK TMS TDI

PT[ij]

TAPC

BYPASS

REGISTER

INSTRUCTION

REGISTER

SCAN

OUT

SCAN

IN

BSC

BDC DCC

SCAN

OUT

p_in

p_ts

p_out

SCAN

IN

BSC

DCC

BDC

PL[ij]

p_ts

p_out

p_in

PLC

ARRAY

p_in

p_out

p_ts

BSC

BDC

PR[ij]

DCC

SCAN

IN

SCAN

OUT

p_out

p_ts

p_in

BSC

DCC BDC

SCAN

OUT

SCAN

IN

PB[ij]

5-5972(F)

Key: BSC = boundary-scan cell, BDC = bidirectional data cell, and

DCC = data control cell.

Figure 25. Printed-Circuit Board with Boundary-

Scan Circuitry

39

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