SPHE8200A View Datasheet(PDF) - Unspecified
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SPHE8200A Datasheet PDF : 40 Pages
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Preliminary
SPHE8200A
5.13. Audio Interface
For power-constrained applications SPHE8200 also implements
The audio interface is in charge of servicing DSP and maintaining
SDRAM power-down modes to save dynamic operating power.
all audio-related tasks. It will buffer the DSP processed audio
playback data and format them to audio DAC required format.
5.17. Sub-picture Decoder
tial GY Memory
fiden OLO C Interface
Buffer
control
Audio
work
buffer
IEC958
digital input
interface
ADC ctrl
IEC-958 input
digital audio input
ADC analog in
PCM
playback
digital audio output
n N IN IEC958
IEC-958 output
o H Figure 5-11: Audio Interface architecture
s C EC ISE SPHE8200 support following audio DAC format combinations:
32k 44.1k 48k
lu T D Y 256fs ok ok ok
np IC N L 384fs ok ok ok
64k 88.2k 96k 192k
ok
ok
ok
ok
ok
ok
ok
ok
A N Data alignment
u N H O LRCK frame width
S N C Data bits
U R E Data sign extension
Left adjust, I2S, normal format
16b, 24b, 32b, 64b
16b, 18b, 20b, 24b
zero-extended, sign-extended
S E S 5.14. Integrated Audio Quality ADC
r U The embedded ADC is a 2-channel 64fs over-sampling ADC
o M of12-bit quality. If required it could operate under 128fs
F & over-sampling.
For DVD and SVCD sub-picture content SPHE8200 includes an
advanced multi-format sub-picture decoder. It could support
real-time decode and display from raw sub-picture bitstream.
Vertical interpolation is supported for PAL/NTSC translation or
special effect.
5.18. On Screen Display
The on screen display (OSD) function of the SPHE8200 provides
an overlay bitmap graphics on the final TV display. Applications
can use this function to display specific information over the video
display plane without operating on the video source.
The SPHE8200 can display multiple OSD regions on a single
display frame, where every OSD regions can be in different size,
location and color format. The OSD hardware supports 4, 16,
256 indexed color or 16-bit direct color. OSD regions are stored
in main memory before display. During display, OSD decoder
would read these header and data and interpret to be a graphic
data that overlay with video to be output to the display interface.
5.19. Display Interface
The display interface of SPHE8200 integrates the video content
generated from video-post-processing, sub-picture-decoder and
on-screen-display modules. It also performs content cropping,
underflow and overflow detection, and overall bright/contrast
adjustment.
blank (black)
Video
active
Sub-picture
active
(1.0 - sup_blend_factor)
OSD
active
5.15. I/O Processor
Video processed
source data
TV data
output
The SPHE8200 includes an 8-bit micro-controller to handle most
I/O jobs. IR, VFD and other slow devices can be interfaced using
sub-picture source data
(1.0 - osd_blend_factor)
(sup_blend_factor)
this I/O processor.
OSD source
(osd_blend_factor)
5.16. SDRAM Controller
SDRAM controller in SPHE8200 is very flexible and powerful. It
Figure 5-12: Display pipeline
was designed to meet different SDRAM timing requirement while
achieving maximum performance. SDRAM tasks are optimized for
maximum system performance. DRAM refreshing is issued
automatically whenever required or SDRAM interface is idle for a
given time.
© Sunplus Technology Co., Ltd.
22
Proprietary & Confidential
OCT. 07, 2003
Preliminary Version: 0.2
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