SPHE8200A View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
SPHE8200A Datasheet PDF : 40 Pages
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Preliminary
SPHE8200A
(Recommended condition for DVD playback is listed in typical condition with f=121.5MHz)
Parameter
Symbol
Min
Typ
Max
Units
Row active to row active delay
tRRD
1
2
4 *1
System clock cycle
RAS to CAS delay
tRCD
1
2
4 *1
System clock cycle
Row precharge time
tRP
Row active time
tRAS
l Y Row cycle time
tRC
tia G Last data in to new column address delay
tCDL
Column address to column address delay
tCCD
n O CLK cycle time *2
tCC
e L CLK to valid SDRAM output delay *2
tSAC
fid O C SDRAM output data hold time *2
tOH
CLK high pulse width *3
tCH
n N IN CLK low pulse width *3
tCL
CLK to SDRAM output Low-Z
tSLZ
o H CLK to SDRAM output High-Z
tSHZ
E *1 Using maximum values may limit system performance.
s C EC IS *2Width of data window can be estimated from (tCC-tSAC+tOH).
*3 Width of clock pulse depends on system clock cycle.
lu T D Y 6.4.2. ROM / flash interface timing diagrams
np IC N L ROM Compatible Mode
1
2
4 *1
System clock cycle
1
5
8 *1
System clock cycle
1
8
32 *1
System clock cycle
1
1
4 *1
System clock cycle
1
1
1
System clock cycle
6
8.2
1000
ns
-
6.0
6.5
ns
1
2
-
ns
-
3
-
ns
-
3
-
ns
-
1.0
(tCC)
ns
-
6.0
(tSAC)
ns
u N HA ON CSB
S UN RC E ADDR[]
S E S OEB
r U WEB
Fo & M DATA[]
tACCESS
Address (read)
tACCESS
Address (write)
tDS
tDH
Data (read)
tWES
tWEH
DATA (for write)
Figure 6-1: ROM / flash interface ROM mode access timing
Parameter
Symbol
Min
Typ
ROM / SRAM / flash access time
tACCESS
2
8 *1
Data setup time for read
tDS
5
-
Data hold time for read
tDH
0
-
Address/data setup time before write strobe
tWS
0
1
Address/data setup time after write strobe
tWH
0
1
*1 Recommended value when f=121.5MHz
Max
31
-
-
31
31
Units
System clock cycle
ns
ns
System clock cycle
System clock cycle
© Sunplus Technology Co., Ltd.
26
Proprietary & Confidential
OCT. 07, 2003
Preliminary Version: 0.2
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