SPHE8200A View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
SPHE8200A Datasheet PDF : 40 Pages
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Preliminary
SPHE8200A
ISA Compatible Mode
CSB
tACCESS
tACCESS
ADDR[]
l Y OEB
tia G WEB
n O IO_RDY
e L DATA[]
Address (read)
tWAIT
tOH
tIH
Address (write)
tWES
tWEH
tWAIT
tOH
tIH
Data (read)
Data (write)
nfid NO INC Figure 6-2: ROM / flash interface ISA mode access timing
Parameter
Symbol
Min
Typ
o H E ISA access time *1
tACCESS
2
-
s C EC IS IO_RDY wait time
tWAIT
0
-
Output hold time
tOH
1
-
Input hold time
tIH
0
-
lu T D Y Address/data setup time before write strobe
tWS
0
1
np IC N L Address/data setup time after write strobe
tWH
0
1
*1 After this period of time IO_RDY_B must be stable and indicates correct status of target device.
Max
31
1000
-
-
31
31
Units
System clock cycle
ns
System clock cycle
ns
System clock cycle
System clock cycle
u N HA N 6.4.3. Audio interface timing diagrams
S N O Some audio interface configuration timing diagrams are shown below.
SU ERC SE BCK
or M U LRCK
F &AUDATA[]
01
22 23 0 1 2
22 23
left channel
right channel
23 22 21 2 1 0 23 22 21 2 1 0
MSB
LSB MSB
LSB
Figure 6-3: Normal mode / 24bit data / 24bit frame / MSB first
BCK
LRCK
AUDATA[]
01
89
30 31 0 1
30 31 0
left channel
23 22 21 2
MSB
10
LSB
right channel
210
Figure 6-4: Right justified (normal) mode / 24bit data / 32bit frame / MSB first
© Sunplus Technology Co., Ltd.
27
Proprietary & Confidential
OCT. 07, 2003
Preliminary Version: 0.2
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