CP2120 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

CP2120

SPI TO I2C BRIDGE AND GPIO PORT EXPANDER

Silicon Laboratories 

5.2.2. Read From Internal Register

CP2120

SPI Master COMMAND

0x21

REGISTER

Address

Don’t Care

CP2120

REGISTER

DATA

A Read from Internal Register command retrieves the current value of one of the CP2120's internal registers. The

command begins with the command byte, 0x21, followed by the internal register address. This byte is followed by

the transmission of a "don't care" byte, which can be of any value and is ignored by the CP2120. After the "don't

care" byte, the internal register value is transmitted across the MISO line.

5.3. SPI Byte Orientation

The SPI Configuration command configures the bit orientation of transfers across the SPI bus to one of two states.

If SPI transmits most-significant-bit first, bit 7 is transmitted first. If SPI transmits least-significant-bit first, bit 0 is

transmitted first.

5.3.1. SPI Configuration

SPI Master

COMMAND

0x18

SPI

CONFIGURATION

The command begins with the command byte (0x18), followed by SPI Configuration byte, which should equal one

of the values shown in the following table. Any values other than those listed in the table are ignored.

Byte Value

0x81

0x42

5.4. SPI Timing Diagrams

Configuration

Most Significant Bit First

Least Significant Bit First

NSS

TSE

SCK*

MOSI

TSEZ

MISO

TCKH

TSIS

TSOH

TCKL

TSIH

Figure 4. SPI Slave Timing

TSD

TSLH

TSDZ

Rev. 1.0

11

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