DS17285(1998) View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated
Part Name
Description
Manufacturer
DS17285 Datasheet PDF : 32 Pages
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DS17285/DS17287
REGISTER B
MSB
BIT 7 BIT 6 BIT 5
SET PIE AIE
BIT 4
UIE
BIT 3
SQWE
BIT 2
DM
LSB
BIT 1 BIT 0
24/12 DSE
SET – When the SET bit is a zero, the update transfer
functions normally by advancing the counts once per
second. When the SET bit is written to a one, any update
transfer is inhibited and the program can initialize the
time and calendar bytes without an update occurring in
the midst of initializing. Read cycles can be executed in
a similar manner. SET is a read/write bit that is not modi-
fied by internal functions of the DS17285/DS17287.
PIE – The Periodic Interrupt Enable bit is a read/write bit
which allows the Periodic Interrupt Flag (PF) bit in Reg-
ister C to drive the IRQ pin low. When the PIE bit is set to
one, periodic interrupts are generated by driving the
IRQ pin low at a rate specified by the RS3–RS0 bits of
Register A. A zero in the PIE bit blocks the IRQ output
from being driven by a periodic interrupt, but the Peri-
odic Flag (PF) bit is still set at the periodic rate. PIE is not
modified by any internal DS17285/DS17287 functions.
AIE – The Alarm Interrupt Enable (AIE) bit is a read/
write bit which, when set to a one, permits the Alarm
Flag (AF) bit in register C to assert IRQ. An alarm inter-
rupt occurs for each second that the three time bytes
equal the three alarm bytes including a “don’t care”
alarm code of binary 11XXXXXX. When the AIE bit is
set to zero, the AF bit does not initiate the IRQ signal.
The internal functions of the DS17285/DS17287 do not
affect the AIE bit.
UIE – The Update Ended Interrupt Enable (UIE) bit is a
read/write that enables the Update End Flag (UF) bit in
Register C to assert IRQ. The SET bit going high clears
the UIE bit.
SQWE – When the Square Wave Enable (SQWE) bit is
set to a one and E32K=0, a square wave signal at the
frequency set by the rate–selection bits RS3 through
RS0 is driven out on the SQW pin. When the SQWE bit
is set to zero and E32K=0, the SQW pin is held low.
SQWE is a read/write bit. SQWE is set to a one when
VCC is powered up.
DM – The Data Mode (DM) bit indicates whether time
and calendar information is in binary or BCD format.
The DM bit is set by the program to the appropriate for-
mat and can be read as required. This bit is not modified
by internal functions. A one in DM signifies binary data
while a zero in DM specifies Binary Coded Decimal
(BCD) data.
24/12 – The 24/12 control bit establishes the format of
the hours byte. A one indicates the 24–hour mode and a
zero indicates the 12–hour mode. This bit is read/write.
DSE – The Daylight Savings Enable (DSE) bit is a read/
write bit which enables two special updates when DSE
is set to one. On the first Sunday in April the time incre-
ments from 1:59:59 AM to 3:00:00 AM. On the last
Sunday in October when the time first reaches 1:59:59
AM it changes to 1:00:00 AM. These special updates do
not occur when the DSE bit is a zero. This bit is not
affected by internal functions.
REGISTER C
MSB
BIT 7 BIT 6
IRQF PF
BIT 5
AF
BIT 4
UF
BIT 3
0
BIT 2
0
BIT 1
0
LSB
BIT 0
0
IRQF – The Interrupt Request Flag (IRQF) bit is set to a
one when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
WF = WIE = 1
KF = KSE= 1
RF = RIE = 1
i.e., IRQF = (PF • PIE) + (AF • AIE) + (UF • UIE) +
(WF • WIE) + (KF • KSE) + (RF • RIE)
Any time the IRQF bit is a one, the IRQ pin is driven low.
Flag bits PF, AF, and UF are cleared after Register C is
read by the program.
PF – The Periodic Interrupt Flag (PF) is a read–only bit
which is set to a one when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0
bits establish the periodic rate. PF is set to a one inde-
pendent of the state of the PIE bit. When both PF and
PIE are ones, the IRQ signal is active and will set the
IRQF bit. The PF bit is cleared by a software read of
Register C.
AF – A one in the Alarm Interrupt Flag (AF) bit indicates
that the current time has matched the alarm time. If the
AIE bit is also a one, the IRQ pin will go low and a one will
appear in the IRQF bit. A read of Register C will
clear AF.
030598 11/32
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