DSP56011 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56011 Datasheet PDF : 82 Pages
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Signal/Connection Descriptions
Serial Host Interface (SHI)
SERIAL HOST INTERFACE (SHI)
The SHI has five I/O signals that can be configured to allow the SHI to operate in
either SPI or I2C mode.
PRELIMINARY Signal
Name
SCK
SCL
Table 1-7 Serial Host Interface (SHI) Signals
Signal
Type
State
during
Reset
Signal Description
Input or
Output
Input or
Output
Tri-stated
SPI Serial Clock—The SCK signal is an output when the SPI
is configured as a master, and a Schmitt-trigger input when
the SPI is configured as a slave. When the SPI is configured as
a master, the SCK signal is derived from the internal SHI
clock generator. When the SPI is configured as a slave, the
SCK signal is an input, and the clock signal from the external
master synchronizes the data transfer. The SCK signal is
ignored by the SPI if it is defined as a slave and the Slave
Select (SS) signal is not asserted. In both the master and slave
SPI devices, data is shifted on one edge of the SCK signal and
is sampled on the opposite edge where data is stable. Edge
polarity is determined by the SPI transfer protocol. The
maximum allowed internally generated bit clock frequency is
fosc/4 for the SPI mode, where fosc is the clock on EXTAL.
The maximum allowed externally generated bit clock
frequency is fosc/3 for the SPI mode.
I2C Serial Clock—SCL carries the clock for I2C bus
transactions in the I2C mode. SCL is a Schmitt-trigger input
when configured as a slave, and an open-drain output when
configured as a master. SCL should be connected to VCC
through a pull-up resistor. The maximum allowed internally
generated bit clock frequency is fosc/6 for the I2C mode
where fosc is the clock on EXTAL. The maximum allowed
externally generated bit clock frequency is fosc/5 for the I2C
mode.
An external pull-up resistor is not required.
1-12
Preliminary Information
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
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