DSP56011 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56011 Datasheet PDF : 82 Pages
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Specifications
AC Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS
The timing waveforms in the AC Electrical Characteristics are tested with a VIL
P R E L I M I N A R Y maximumof0.5VandaVIHminimumof2.4Vforallinputs,exceptEXTAL,
RESET, MODA, MODB, MODC, ACI, and SHI inputs (MOSI/HA0, SS/HA2,
MISO/SDA, SCK/SCL, HREQ). These inputs are tested using the input levels set
forth in the DC Electrical Characteristics. AC timing specifications that are
referenced to a device input signal are measured in production with respect to the
50% point of the respective input signal’s transition. DSP56011 output levels are
measured with the production test machine VOL and VOH reference levels set at
0.8 V and 2.0 V, respectively.
All output delays are given for a 50 pF load unless otherwise specified.
For load capacitance greater than 50 pF, the drive capability of the output pins
typically decreases linearly:
1. At 1.5 ns per 10 pF of additional capacitance at all output pins except
MOSI/HA0, MISO/SDA, SCK/SCL, HREQ
2. At 1.0 ns per 10 pF of additional capacitance at output pins MOSI/HA0,
MISO/SDA, SCK/SCL, HREQ (in SPI mode only)
INTERNAL CLOCKS
Table 2-4 Internal Clocks
Characteristics
Internal operation frequency
Internal clock high period
• with PLL disabled1
• with PLL enabled and MF ≤ 4
• with PLL enabled and MF > 4
Internal clock low period
• with PLL disabled (see Note)
• with PLL enabled and MF ≤ 4
• with PLL enabled and MF > 4
Symbol
F
TH
TL
Expression
Minimum
0
Maximum
95 MHz
ETHminimum
0.48 × TC
0.467 × TC
ETLminimum
0.48 × TC
0.467 × TC
ETHmaximum
0.52 × TC
0.533 × TC
ETLmaximum
0.52 × TC
0.533 × TC
Internal clock cycle time
TC
(DF × ETC)/MF
Instruction cycle time
ICYC
2 × TC
Note: See Table 2-5 on page 2-5 for External Clock (ET) specifications.
Preliminary Information
2-4
DSP56011 Technical Data Sheet, Rev. 1
MOTOROLA
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