DSP56321 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56321 Datasheet PDF : 84 Pages
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AC Electrical Characteristics
A[0–17]
AA[0–3]
WR
RD
101
114
100
107
102
118
103
119
TA
D[0–23]
108
109
Data
Out
Note: Address lines A[0–17] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
Figure 2-11. SRAM Write Access
2.4.5.2 Asynchronous Bus Arbitration Timings
Table 2-9. Asynchronous Bus Timings
No.
Characteristics
Expression
200 MHz 220 MHz
Min Max Min Max
240 MHz
275 Mhz Uni
Min Max Min Max t
250 BB assertion window from BG input
deassertion.
2.5 × Tc + 5 — 17.5 — 16.4 — 15.4 — 14.1 ns
251 Delay from BB assertion to BG assertion
2 × Tc + 5
15 — 14.1 — 13.3 — 12.27 — ns
Notes: 1. Bit 13 in the Operating Mode Register must be set to enable Asynchronous Arbitration mode.
2. To guarantee timings 250 and 251, it is recommended that you assert non-overlapping BG inputs to different DSP56300
devices (on the same bus), as shown in Figure 2-12, where BG1 is the BG signal for one DSP56300 device while BG2 is the
BG signal for a second DSP56300 device.
Freescale Semiconductor
DSP56321 Technical Data, Rev. 11
2-13
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