DSP56321 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56321

24-Bit Digital Signal Processor

Freescale Semiconductor 

Specifications

BG1

BB

250

BG2

251

250+251

Figure 2-12. Asynchronous Bus Arbitration Timing

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These

synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this

delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is deasserted. This is the

reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other

DSP56300 components that are potential masters on the same bus. If BG input is asserted before that time, and BG

is asserted and BB is deasserted, another DSP56300 component may assume mastership at the same time.

Therefore, some non-overlap period between one BG input active to another BG input active is required. Timing 251

ensures that overlaps are avoided.

2.4.6 Host Interface Timing

Table 2-10. Host Interface Timings1,2,12

200 MHz

No.

Characteristic10

Expression

Min Max

317 Read data strobe assertion width5

HACK assertion width

TC + 4.95 9.95 —

318 Read data strobe deassertion width5

HACK deassertion width

4.95 —

319 Read data strobe deassertion width5 after

2.5 × TC + 3.3 15.8 —

“Last Data Register” reads8,11, or between two

consecutive CVR, ICR, or ISR reads3

HACK deassertion width after “Last Data

Register” reads8,11

320 Write data strobe assertion width6

6.6 —

321 Write data strobe deassertion width8

HACK write deassertion width

• after ICR, CVR and “Last Data Register” 2.5 × TC + 3.3 15.8 —

writes

220 MHz

Min Max

9.05 —

4.5 —

14.7 —

6.0 —

14.7 —

240 MHz

275 MHz Uni

Min Max Min Max t

8.3 — 7.77 — ns

4.13 — 4.0 — ns

13.7 — 12.39 — ns

5.5 — 5.1 — ns

13.7 — 12.39 — ns

• after IVR writes, or

after TXH:TXM:TXL writes (with HLEND=

0), or

after TXL:TXM:TXH writes (with HLEND =

1)

322 HAS assertion width

8.25 — 7.5 — 6.88 — 6.28 — ns

4.95 — 4.5 — 4.13 — 4.0 — ns

2-14

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor

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