DSP56321 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56321 Datasheet PDF : 84 Pages
| |||
Specifications
Table 2-8. SRAM Timing (Continued)
No. Characteristics Symbol
Expression1
200 MHz 220 MHz 240 MHz 275 MHz
Unit
Min Max Min Max Min Max Min Max
115 Address valid to RD
assertion
—
0.5 × TC −2.0
0.5 — 0.3 — 0.1 — –0.18 — ns
116 RD assertion pulse width
—
(WS + 0.25) × TC −3.0 13.25 — 11.59 — 10.55 — 8.81 — ns
[WS ≥ 3]
117 RD deassertion to
address not valid
—
1.25 × TC −4.0
2.25 — 1.69 — 1.21 — 0.54 — ns
[3 ≤WS ≤7]
2.25 × TC −4.0
[WS ≥ 8]
7.25 — 6.24 — 5.38 — 4.18 — ns
118 TA setup before RD or
—
WR deassertion5
0.25 × TC + 2.0
3.25 — 3.14 — 3.04 — 2.91 — ns
119 TA hold after RD or WR
—
deassertion
0
—
0
—
0
—
0
— ns
Notes: 1. WS is the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For example,
for a category of [3 ≤WS ≤7] timing is specified for 3 wait states.) Three wait states is the minimum value otherwise.
2. Timings 100 and 107 are guaranteed by design, not tested.
3. All timings are measured from 0.5 × VCCQH to 0.5 × VCCQH.
4. The WS number applies to the access in which the deassertion of WR occurs and assumes the next access uses a minimal
number of wait states.
5. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted.
A[0–17]
AA[0–3]
RD
WR
100
113
116
117
105
106
104
118
119
TA
D[0–23]
Note: Address lines A[0–17] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
Figure 2-10. SRAM Read Access
Data
In
2-12
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
Share Link: 