MT41J128M View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT41J128M

DDR3 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR3 SDRAM

Asynchronous ODT Mode

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)

There is a transition period around power-down entry (PDE) where the DRAM’s ODT

may exhibit either synchronous or asynchronous behavior. This transition period oc-

curs if the DLL is selected to be off when in precharge power-down mode by the setting

MR0[12] = 0. Power-down entry begins tANPD prior to CKE first being registered LOW,

and ends when CKE is first registered LOW. tANPD is equal to the greater of ODTLoff +

1tCK or ODTLon + 1tCK. If a REFRESH command has been issued, and it is in progress

when CKE goes LOW, power-down entry ends tRFC after the REFRESH command, rath-

er than when CKE is first registered LOW. Power-down entry then becomes the greater

of tANPD and tRFC - REFRESH command to CKE registered LOW.

ODT assertion during power-down entry results in an RTT change as early as the lesser

of tAONPD (MIN) and ODTLon × tCK + tAON (MIN), or as late as the greater of tAONPD

(MAX) and ODTLon × tCK + tAON (MAX). ODT de-assertion during power-down entry

can result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTLoff × tCK +

tAOF (MIN), or as late as the greater of tAOFPD (MAX) and ODTLoff × tCK + tAOF (MAX).

Table 92 (page 209) summarizes these parameters.

If AL has a large value, the uncertainty of the state of RTT becomes quite large. This is

because ODTLon and ODTLoff are derived from the WL; and WL is equal to CWL + AL.

Figure 119 (page 209) shows three different cases:

• ODT_A: Synchronous behavior before tANPD.

• ODT_B: ODT state changes during the transition period with tAONPD (MIN) <

ODTLon × tCK + tAON (MIN) and tAONPD (MAX) > ODTLon × tCK + tAON (MAX).

• ODT_C: ODT state changes after the transition period with asynchronous behavior.

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN

208

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