MT41J128M View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT41J128M

DDR3 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR3 SDRAM

Asynchronous to Synchronous ODT Mode Transition (Power-

Down Exit)

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

The DRAM’s ODT can exhibit either asynchronous or synchronous behavior during

power-down exit (PDX). This transition period occurs if the DLL is selected to be off

when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins

tANPD prior to CKE first being registered HIGH, and ends tXPDLL after CKE is first reg-

istered HIGH. tANPD is equal to the greater of ODTLoff + 1tCK or ODTLon + 1tCK. The

transition period is tANPD + tXPDLL.

ODT assertion during power-down exit results in an RTT change as early as the lesser of

tAONPD (MIN) and ODTLon × tCK + tAON (MIN), or as late as the greater of tAONPD

(MAX) and ODTLon × tCK + tAON (MAX). ODT de-assertion during power-down exit

may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTLoff × tCK +

tAOF (MIN), or as late as the greater of tAOFPD (MAX) and ODTLoff × tCK + tAOF (MAX).

Table 92 (page 209) summarizes these parameters.

If AL has a large value, the uncertainty of the RTT state becomes quite large. This is be-

cause ODTLon and ODTLoff are derived from WL, and WL is equal to CWL + AL. Fig-

ure 120 (page 211) shows three different cases:

• ODT C: Asynchronous behavior before tANPD.

• ODT B: ODT state changes during the transition period, with tAOFPD (MIN) < ODTL-

off × tCK + tAOF (MIN), and ODTLoff × tCK + tAOF (MAX) > tAOFPD (MAX).

• ODT A: ODT state changes after the transition period with synchronous response.

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN

210

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