MT48LC1M16A1 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC1M16A1 Datasheet PDF : 51 Pages
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OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be
issued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated (see Figure 3).
After opening a row (issuing an ACTIVE com-
mand) a READ or WRITE command may be issued to
that row, subject to the tRCD specification. tRCD
(MIN) should be divided by the clock period and
rounded up to the next whole number to determine
the earliest clock edge after the ACTIVE command on
which a READ or WRITE command can be issued. For
example, a tRCD specification of 20ns with a 125 MHz
clock (8ns period) results in 2.5 clocks rounded to 3.
This is reflected in Figure 4, which covers any case where
2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used
to convert other specification limits from time units to
clock cycles.)
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed, which
results in a reduction of total row access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by tRRD.
CLK
CKE HIGH
CS#
16Mb: x16
IT SDRAM
RAS#
CAS#
WE#
A0-A10
ROW
ADDRESS
BANK 1
BA
BANK 0
Figure 3
Activating a Specific Row
in a Specific Bank
T0
T1
T2
T3
T4
CLK
COMMAND
ACTIVE
NOP
NOP
READ or
WRITE
tRCD
DON’T CARE
Figure 4
EXAMPLE: Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK ≤ 3
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
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