MT48LC1M16A1 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC1M16A1 Datasheet PDF : 51 Pages
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A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that AUTO PRECHARGE was not
activated) and a full-page burst may be truncated with
a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles be-
fore the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
16Mb: x16
IT SDRAM
latency; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until tRP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
t RP
NOP
PRECHARGE
NOP
NOP
X = 0 cycles
BANK
(a or all)
T7
ACTIVE
BANK a,
ROW
DQ
DOUT
n
CAS Latency = 1
DOUT
n+1
DOUT
n+2
DOUT
n+3
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
t RP
NOP
PRECHARGE
NOP
NOP
X = 1 cycle
BANK
(a or all)
T7
ACTIVE
BANK a,
ROW
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 2
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
T7
t RP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
X = 2 cycles
ACTIVE
BANK a,
ROW
DQ
CAS Latency = 3
NOTE: DQM is LOW.
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DON’T CARE
Figure 11
READ to PRECHARGE
17
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©1999, Micron Technology, Inc.
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